公开(公告)号：US08429586B2

公开(公告)日：2013-04-23

申请号：US13424747

申请日：2012-03-20

申请人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl A. Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary S. Delp ,  Scott A. Peterson

发明人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl A. Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary S. Delp ,  Scott A. Peterson

IPC分类号： G06F17/50

CPC分类号： H03K19/1735 ,  G06F2217/64 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807

摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

摘要翻译： 提供了具有多个可固定晶体管的单元的基本单元电路架构，其可配置用于形成逻辑器件以及结构化ASIC内的单端口和双端口存储器件。 通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。 电路架构可以实现单个单元或多个单元内的晶体管的互连。 互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。 此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。 通过具有形成逻辑电路元件，存储器件或二者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，更能适应现代的SoC。