公开(公告)号：US09460253B1

公开(公告)日：2016-10-04

申请号：US14482945

申请日：2014-09-10

Applicant: Xilinx, Inc.

Inventor： Elliott Delaye ,  Ashish Sirasao ,  Krishna Garlapati ,  Bing Tian

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F2217/14 ,  G06F2217/64 ,  G06F2217/66

Abstract: In an example, a method of processing a circuit design includes: determining a first partition in a description of the circuit design having a hierarchy of design objects, the first partition including at least one design object in the hierarchy of design objects; generating a signature for the first partition; querying a database with the signature of the first partition to identify a plurality of predefined implementations of the first partition; and generating an implementation of the circuit design for a target integrated circuit (IC) based on a selected predefined implementation of the plurality of predefined implementations for the first partition.

Abstract translation: 在一个示例中，一种处理电路设计的方法包括：在具有设计对象层级的电路设计的描述中确定第一分区，第一分区包括设计对象层级中的至少一个设计对象; 生成第一分区的签名; 用第一分区的签名查询数据库以识别第一分区的多个预定义的实现; 以及基于用于所述第一分区的所述多个预定义实现的所选择的预定义实现来生成用于目标集成电路（IC）的电路设计的实现。

公开(公告)号：US08910103B2

公开(公告)日：2014-12-09

申请号：US12648099

申请日：2009-12-28

Applicant: Fabio Campi ,  Claudio Mucci ,  Stefano Pucillo ,  Luca Ciccarelli ,  Valentina Nardone

Inventor： Fabio Campi ,  Claudio Mucci ,  Stefano Pucillo ,  Luca Ciccarelli ,  Valentina Nardone

IPC: G06F17/50 ,  G06F15/76 ,  G06F9/30

CPC classification number: G06F17/5068 ,  G06F2217/64

Abstract: A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.

Abstract translation: 一种用于设计用于数字信号处理的加速器的方法，包括通过用固定拓扑预先布置DSP加速器的控制逻辑来定义可完全预编程的软件，以获得完全预先布置的控制逻辑。 该方法还包括通过定制可配置布局区域来定义硬件可编程部分预布置的宏，从而基于与DSP加速器的应用相关的计算内核映射计算逻辑。 因此获得部分预先布置的计算逻辑。

公开(公告)号：US20120286822A1

公开(公告)日：2012-11-15

申请号：US13556074

申请日：2012-07-23

Applicant: Raminda Udaya Madurawe

Inventor： Raminda Udaya Madurawe

IPC: H03K19/173

CPC classification number: G06F17/5068 ,  G06F2217/64

Abstract: An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the data points in the set uniquely matched to a plurality of fixed metal tabs; and selecting a metal tab from a first set of selectable metal tabs for a first data value, or a second set of selectable metal tabs for a second data value for each of the fixed metal tabs; wherein a first set metal tab and a second set metal tab couples each said fixed metal tab to first and second voltages respectively.

Abstract translation: 一种由包括掩模的掩模组制成的集成电路，用于生成由CAD软件定义的金属图案，所述金属图案生成方法包括：读取二进制数据集，所述集合中的数据点与多个固定金属片唯一地匹配; 以及从用于第一数据值的第一组可选金属片选择金属片，或者为每个固定金属片的第二数据值选择第二组可选金属片; 其中第一组金属片和第二组金属片将每个所述固定金属片分别耦合到第一和第二电压。

公开(公告)号：US07895559B2

公开(公告)日：2011-02-22

申请号：US12218672

申请日：2008-07-17

Applicant: Jai P. Bansal

Inventor： Jai P. Bansal

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/64

Abstract: A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.

Abstract translation: 多功能核心基站包括一组功能微电路。 这些微电路用于设计逻辑函数库。 由一个或多个微电路组成的功能宏具有类似于常规标准单元库宏集的固定和完整的物理布局。 除了核心功能宏集之外，库中还定义了主输入/输出缓冲区和常用的单端口和双端口存储器块。 该库包括所有的ASIC综合，仿真和物理设计规则。

公开(公告)号：US07590967B1

公开(公告)日：2009-09-15

申请号：US11669871

申请日：2007-01-31

Applicant: Robert S. Kirk

Inventor： Robert S. Kirk

IPC: G06F17/50

CPC classification number: H03K17/693 ,  G03F1/50 ,  G06F2217/64 ,  H01L21/78 ,  H01L27/11807

Abstract: One embodiment of the present invention provides for a master or universal base and base tooling which addresses the general purpose Structured ASIC requirements. Another embodiment of the present invention provides for a common set of base tooling from which the master/universal base is created as well as additional custom bases with customized selection and quantity of embedded Platform ASIC functions. Embodiments can utilize conventional Structured ASIC architecture and processing and are compatible with traditional probing and packaging.

Abstract translation: 本发明的一个实施例提供了一种主要或通用的基础和基础工具，其满足通用结构化ASIC要求。 本发明的另一个实施例提供了一组通用的基础工具，其中创建了主/通用基座以及附加的定制基础，具有定制的嵌入式平台ASIC功能的选择和数量。 实施例可以利用传统的结构化ASIC架构和处理，并且与传统的探测和封装兼容。

公开(公告)号：US07587686B1

公开(公告)日：2009-09-08

申请号：US11497705

申请日：2006-08-01

Applicant: James G. Schleicher, II

Inventor： James G. Schleicher, II

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/64

Abstract: Circuits and methods use clock gating to reduce power consumption in select parts of a structured ASIC. A clock distribution network includes a deterministic portion, a configurable portion, and one or more clock gating circuits. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal and a clock enable signal to a plurality of predetermined locations on the device. A clock gating circuit, connected with the deterministic portion, may be placed at any of the predetermined locations, or at any location within predetermined areas associated with the predetermined locations. The clock gating circuit produces a gated clock signal output. A configurable portion and/or subportion distributes the gated clock signal output to logic elements. Depending on the value of the clock enable signal, operation of the logic elements may be suspended.

Abstract translation: 电路和方法使用时钟选通来降低结构化ASIC的某些部分的功耗。 时钟分配网络包括确定性部分，可配置部分和一个或多个时钟门控电路。 确定部分采用预定布置的导体段和缓冲器，用于将时钟信号和时钟使能信号分配到设备上的多个预定位置。 与确定性部分连接的时钟门控电路可以放置在任何预定位置处，或者与预定位置相关联的预定区域内的任何位置。 时钟选通电路产生门控时钟信号输出。 可配置部分和/或子部分将门控时钟信号输出分配给逻辑元件。 根据时钟使能信号的值，可能会暂停逻辑元件的操作。

公开(公告)号：US07069523B2

公开(公告)日：2006-06-27

申请号：US10318623

申请日：2002-12-13

Applicant: George Wayne Nation ,  Gary Scott Delp ,  Paul Gary Reuland

Inventor： George Wayne Nation ,  Gary Scott Delp ,  Paul Gary Reuland

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/64

Abstract: A tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit. Given a manufactured slice that has a number of blocks already diffused and logically integrated, the memory generation tool herein automatically considers the available diffused memory and the gate array of the slices to configure and optimize them into a customer's requirements for memory. The memory generation tool has a memory manager, a memory resource database, a memory resource selector, and a memory composer. Together these all interact to generate memories from the available memories within the memory resource database. The memory composer actually generates the RTL logic shells for the memories, and outputs the memory designs in Verilog, VHDL, or other tool synthesis language. Once a memory is created, it is tested. Upon successful testing, the memory manager updates the memory resource database to indicate the successfully tested memory is no longer available as a resource for the generation of further memories. A design integrator may review the memory designs output and further integrate the memory, its timing, testing, etc. with other blocks and functions of the integrated circuit.

Abstract translation: 用于设计集成电路的工具，可优化电路内存储块的位置和时序。 给定已经扩散和逻辑整合的多个块的制造片，这里的存储器生成工具自动考虑片的可用扩散存储器和门阵列，以将其配置和优化成客户对存储器的要求。 存储器生成工具具有存储器管理器，存储器资源数据库，存储器资源选择器和存储器编程器。 这些都一起进行交互以从存储器资源数据库内的可用存储器生成存储器。 内存作曲家实际上为存储器生成RTL逻辑外壳，并以Verilog，VHDL或其他工具合成语言输出内存设计。 一旦创建内存，就会进行测试。 成功测试后，内存管理员更新内存资源数据库，以指示成功测试的内存不再可用作生成更多内存的资源。 设计集成商可以检查存储器设计输出，并将存储器，其定时，测试等与集成电路的其他块和功能进一步集成。

公开(公告)号：US20050108495A1

公开(公告)日：2005-05-19

申请号：US10713492

申请日：2003-11-14

Applicant: Douglas McKenney ,  Steven Emerson

Inventor： Douglas McKenney ,  Steven Emerson

IPC: G06F17/50 ,  G06F12/00

CPC classification number: G06F17/5045 ,  G06F2217/64 ,  G06F2217/68

Abstract: A method for designing and using a partially manufactured semiconductor product is disclosed. The partially manufactured semiconductor product, referred to as a slice, contains a fabric of configurable transistors and at least an area of embedded memory. The method contemplates that a range of processors, processing elements, processing circuits exists which might be manufactured as a hardmacs or configured from the transistor fabric of the slice. The method then evaluates all the memory requirements of all the processors in the range to create a memory superset to be embedded into the slice. The memory superset can then be mapped and routed to a particular memory for one of the processors within the range; ports can be mapped and routed to access the selected portions of the memory superset. If any memory is not used, then it and/or its adjoining transistor fabric can become a landing zone for other functions or registers or memories.

Abstract translation: 公开了一种用于设计和使用部分制造的半导体产品的方法。 部分制造的半导体产品（被称为切片）包含可配置晶体管的结构和至少一个嵌入式存储器的区域。 该方法考虑到存在一些处理器，处理元件，处理电路的范围，其可以被制造为硬片或者由片的晶体管结构配置。 该方法然后评估范围内的所有处理器的所有内存要求，以创建要嵌入到片中的内存超集。 然后，存储器超集可被映射并路由到该范围内的一个处理器的特定存储器; 可以映射和路由端口以访问存储器超集的选定部分。 如果没有使用任何存储器，那么它和/或其相邻的晶体管结构可以成为其他功能或寄存器或存储器的着陆区。

公开(公告)号：US20040117744A1

公开(公告)日：2004-06-17

申请号：US10318623

申请日：2002-12-13

Applicant: LSI LOGIC CORPORATION

Inventor： George Wayne Nation ,  Gary Scott Delp ,  Paul Gary Reuland

IPC: G06F017/50

CPC classification number: G06F17/5045 ,  G06F2217/64

Abstract: A tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit. Given a manufactured slice that has a number of blocks already diffused and logically integrated, the memory generation tool herein automatically considers the available diffused memory and the gate array of the slices to configure and optimize them into a customer's requirements for memory. The memory generation tool has a memory manager, a memory resource database, a memory resource selector, and a memory composer. Together these all interact to generate memories from the available memories within the memory resource database. The memory composer actually generates the RTL logic shells for the memories, and outputs the memory designs in Verilog, VHDL, or other tool synthesis language. Once a memory is created, it is tested. Upon successful testing, the memory manager updates the memory resource database to indicate the successfully tested memory is no longer available as a resource for the generation of further memories. A design integrator may review the memory designs output and further integrate the memory, its timing, testing, etc. with other blocks and functions of the integrated circuit.

Abstract translation: 用于设计集成电路的工具，可优化电路内存储块的位置和时序。 给定已经扩散和逻辑整合的多个块的制造片，这里的存储器生成工具自动考虑片的可用扩散存储器和门阵列，以将其配置和优化成客户对存储器的要求。 存储器生成工具具有存储器管理器，存储器资源数据库，存储器资源选择器和存储器编程器。 这些都一起进行交互以从存储器资源数据库内的可用存储器生成存储器。 内存作曲家实际上为存储器生成RTL逻辑外壳，并以Verilog，VHDL或其他工具合成语言输出内存设计。 一旦创建内存，就会进行测试。 成功测试后，内存管理员更新内存资源数据库，以指示成功测试的内存不再可用作生成更多内存的资源。 设计集成商可以检查存储器设计输出，并将存储器，其定时，测试等与集成电路的其他块和功能进一步集成。

公开(公告)号：US09760673B2

公开(公告)日：2017-09-12

申请号：US15012331

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric D. Hunt-Schroeder ,  John R. Goss ,  Igor Arsovski ,  Paul J. Grzymkowski

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/64

Abstract: Various embodiments include approaches for analyzing a customer design for an application specific integrated circuit (ASIC). In some cases, an approach includes: determining performance requirements of the customer design; querying a test screen database for the performance requirements of the customer design, the test screen database having failure thresholds and associated test screens for detecting the failure thresholds for a set of ASIC devices; generating a filter database including select failure thresholds and associated test screens for the performance requirements of the customer design; and selecting a set of test screens from the filter database based upon a yield cost criteria in forming the ASIC.