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    Logic-based eDRAM using local interconnects to reduce impact of extension contact parasitics
    1.
    发明授权
    Logic-based eDRAM using local interconnects to reduce impact of extension contact parasitics 有权
    基于逻辑的eDRAM使用局部互连来减少延长触点寄生效应的影响

    公开(公告)号：US08283713B2

    公开(公告)日：2012-10-09

    申请号：US13046973

    申请日：2011-03-14

    申请人： John G. Jansen ,  Chi-Yi Kao ,  Ce Chen ,  Shahriar Moinian

    发明人： John G. Jansen ,  Chi-Yi Kao ,  Ce Chen ,  Shahriar Moinian

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10894 ,  H01L27/10855 ,  H01L27/10882 ,  H01L27/10888 ,  H01L27/10897

    摘要： An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.

    摘要翻译： 电子器件包括位于衬底上方的有源层，有源层具有逻辑电路和eDRAM单元。 电子器件还包括位于有源层上的第一金属化级，其提供逻辑互连和金属电容器板。 逻辑互连连接到逻辑电路，金属电容器板连接到eDRAM单元。 电子设备还包括位于第一金属化级别上的第二金属化级别，其提供连接到至少一个逻辑互连的互连线以及连接到eDRAM单元的位线。 还包括制造电子装置的方法。

    LOGIC-BASED eDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS
    2.
    发明申请
    LOGIC-BASED eDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS 有权
    基于逻辑的eDRAM使用本地互连来减少扩展联系人的影响

    公开(公告)号：US20110298026A1

    公开(公告)日：2011-12-08

    申请号：US13046973

    申请日：2011-03-14

    申请人： John G. Jansen ,  Chi-Yi Kao ,  Ce Chen ,  Shahriar Moinian

    发明人： John G. Jansen ,  Chi-Yi Kao ,  Ce Chen ,  Shahriar Moinian

    IPC分类号： H01L27/108 ,  H01L21/28

    CPC分类号： H01L27/10894 ,  H01L27/10855 ,  H01L27/10882 ,  H01L27/10888 ,  H01L27/10897

    摘要： An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.

    摘要翻译： 电子器件包括位于衬底上方的有源层，有源层具有逻辑电路和eDRAM单元。 电子器件还包括位于有源层上的第一金属化级，其提供逻辑互连和金属电容器板。 逻辑互连连接到逻辑电路，金属电容器板连接到eDRAM单元。 电子设备还包括位于第一金属化级别上的第二金属化级别，其提供连接到至少一个逻辑互连的互连线以及连接到eDRAM单元的位线。 还包括制造电子装置的方法。