公开(公告)号：US08283713B2

公开(公告)日：2012-10-09

申请号：US13046973

申请日：2011-03-14

申请人： John G. Jansen ,  Chi-Yi Kao ,  Ce Chen ,  Shahriar Moinian

发明人： John G. Jansen ,  Chi-Yi Kao ,  Ce Chen ,  Shahriar Moinian

IPC分类号： H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10855 ,  H01L27/10882 ,  H01L27/10888 ,  H01L27/10897

摘要： An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.

摘要翻译： 电子器件包括位于衬底上方的有源层，有源层具有逻辑电路和eDRAM单元。 电子器件还包括位于有源层上的第一金属化级，其提供逻辑互连和金属电容器板。 逻辑互连连接到逻辑电路，金属电容器板连接到eDRAM单元。 电子设备还包括位于第一金属化级别上的第二金属化级别，其提供连接到至少一个逻辑互连的互连线以及连接到eDRAM单元的位线。 还包括制造电子装置的方法。

公开(公告)号：US20110298026A1

公开(公告)日：2011-12-08

申请号：US13046973

申请日：2011-03-14

申请人： John G. Jansen ,  Chi-Yi Kao ,  Ce Chen ,  Shahriar Moinian

发明人： John G. Jansen ,  Chi-Yi Kao ,  Ce Chen ,  Shahriar Moinian

IPC分类号： H01L27/108 ,  H01L21/28

CPC分类号： H01L27/10894 ,  H01L27/10855 ,  H01L27/10882 ,  H01L27/10888 ,  H01L27/10897

摘要： An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.

摘要翻译： 电子器件包括位于衬底上方的有源层，有源层具有逻辑电路和eDRAM单元。 电子器件还包括位于有源层上的第一金属化级，其提供逻辑互连和金属电容器板。 逻辑互连连接到逻辑电路，金属电容器板连接到eDRAM单元。 电子设备还包括位于第一金属化级别上的第二金属化级别，其提供连接到至少一个逻辑互连的互连线以及连接到eDRAM单元的位线。 还包括制造电子装置的方法。

公开(公告)号：US20080074229A1

公开(公告)日：2008-03-27

申请号：US11535501

申请日：2006-09-27

申请人： Shahriar Moinian ,  John E. Scoggins

发明人： Shahriar Moinian ,  John E. Scoggins

IPC分类号： H01F5/00

CPC分类号： H01F17/0006 ,  H01F2017/0046 ,  H01F2017/008 ,  H01F2021/125 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inductor device in an integrated circuit includes a first winding portion, a bridge portion and a second winding portion. The integrated circuit has a first, a second, a third and a fourth metallization level. The first winding portion comprises a first metal line formed on the first metallization level and a second metal line formed on the second metallization level, the first metal line being electrically connected in parallel with the second metal line. The bridge portion comprises a third metal line formed on the third metallization level and a fourth metal line formed on the fourth metallization level, the third metal line being electrically connected in parallel with the fourth metal line. The second winding portion comprises a fifth metal line formed on the first metallization level and a sixth metal line formed on the second metallization level, the fifth metal line being electrically connected in parallel with the sixth metal line. The bridge portion electrically connects the first winding portion to the second winding portion.

摘要翻译： 集成电路中的电感器件包括第一绕组部分，桥接部分和第二绕组部分。 集成电路具有第一，第二，第三和第四金属化层。 第一绕组部分包括形成在第一金属化层上的第一金属线和形成在第二金属化层上的第二金属线，第一金属线与第二金属线并联电连接。 桥接部分包括形成在第三金属化层上的第三金属线和形成在第四金属化层上的第四金属线，第三金属线与第四金属线并联电连接。 第二绕组部分包括形成在第一金属化层上的第五金属线和形成在第二金属化层上的第六金属线，第五金属线与第六金属线并联电连接。 桥接部分将第一绕组部分电连接到第二绕组部分。

公开(公告)号：US20060107243A1

公开(公告)日：2006-05-18

申请号：US10992031

申请日：2004-11-18

申请人： James Chlipala ,  Shahriar Moinian

发明人： James Chlipala ,  Shahriar Moinian

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L21/76224 ,  H01L27/0207

摘要： The present invention provides a method for manufacturing a semiconductor device, comprising: determining an isolation structure stress effect of a first semiconductor device, determining an optical proximity effect of a second semiconductor device, selecting a modeling design parameter such that the isolation structure stress effect is offset against the optical proximity effect on a fabrication model, and using the selected design parameter to construct a third semiconductor device.

摘要翻译： 本发明提供一种制造半导体器件的方法，包括：确定第一半导体器件的隔离结构应力效应，确定第二半导体器件的光学邻近效应，选择建模设计参数，使得隔离结构应力效应为 抵消制造模型上的光学邻近效应，并且使用所选择的设计参数来构造第三半导体器件。

公开(公告)号：US20100314713A1

公开(公告)日：2010-12-16

申请号：US12516301

申请日：2009-03-18

申请人： Weiwei Mao ,  Shahriar Moinian ,  Kenneth Wade Paist ,  William B. Wilson

发明人： Weiwei Mao ,  Shahriar Moinian ,  Kenneth Wade Paist ,  William B. Wilson

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/70

CPC分类号： H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.

摘要翻译： 提供了一种IC电感器结构，其包括形成在半导体衬底上的第一电感器元件和形成在靠近第一电感器元件的半导体衬底上的至少第二电感器元件。 第一电感器元件具有与其相关联的第一有效磁场方向，并且第二电感器元件具有与其相关联的第二有效磁场方向。 第一和第二电感器元件相对于彼此定向，以便在第一和第二有效磁场方向之间产生非零角度。

公开(公告)号：US07480874B2

公开(公告)日：2009-01-20

申请号：US11198930

申请日：2005-08-05

申请人： Kausar Banoo ,  Seung H. Kang ,  Shahriar Moinian ,  Blane A. Musser ,  John A. Pantone

发明人： Kausar Banoo ,  Seung H. Kang ,  Shahriar Moinian ,  Blane A. Musser ,  John A. Pantone

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Techniques are presented for reliability analysis of integrated circuits. A circuit data file including a connectivity network with appended parasitic information is obtained. Circuit performance is simulated, based on the data file, to obtain simulated currents for metallic conductive paths of the circuit. Contextual representations of the paths are determined, and reliability analysis is performed on the contextual representations. The analysis can relate, for example, to electromigration, joule-heating, and/or fusing. The results of the analysis can be provided, for example, in the form of a report including recommended changes, such as width increases, to wires for which it is determined that reliability issues exist.

摘要翻译： 介绍了集成电路可靠性分析的技术。 获得包括具有附加寄生信息的连通性网络的电路数据文件。 基于数据文件模拟电路性能，以获得电路的金属导电路径的模拟电流。 确定路径的上下文表示，并对上下文表示进行可靠性分析。 该分析可以涉及例如电迁移，焦耳加热和/或熔化。 分析结果可以例如以报告的形式提供，包括推荐的变化（例如宽度增加）到确定可靠性问题的电线。

公开(公告)号：US20050023645A1

公开(公告)日：2005-02-03

申请号：US10918981

申请日：2004-08-16

申请人： Shye Shapira ,  Debra Johnson ,  Shahriar Moinian

发明人： Shye Shapira ,  Debra Johnson ,  Shahriar Moinian

IPC分类号： H01L29/93 ,  H01L29/94 ,  H01L21/20

CPC分类号： H01L29/94 ,  H01L29/93

摘要： The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.

摘要翻译： 本发明提供一种变容二极管及其制造方法。 在示例性实施例中，变容二极管分别包括第一和第二导电类型的半导体衬底和阱。 阱中的导电区域具有与阱相同的导电类型，但是具有比阱更低的电阻率。 阱的至少一部分在导电区域的至少两侧之间以及在该阱上的导电层的外周界所描绘的区域之间。 这种变容二极管具有较低的串联电阻，因此具有增加的品质因数。

公开(公告)号：US06657281B1

公开(公告)日：2003-12-02

申请号：US09631755

申请日：2000-08-03

申请人： Yih-Feng Chyan ,  Chunchieh Huang ,  Chung Wai Leung ,  Yi Ma ,  Shahriar Moinian

发明人： Yih-Feng Chyan ,  Chunchieh Huang ,  Chung Wai Leung ,  Yi Ma ,  Shahriar Moinian

IPC分类号： H01L27082

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/0804

摘要： The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.

摘要翻译： 本发明提供一种位于半导体晶片基板上的双极晶体管。 双极晶体管可以包括位于半导体晶片衬底中的集电极，位于集电极中的基极和位于基极上并与基极的至少一部分接触的发射极，其中发射极具有位于其中的低K层 。 例如，低K层可以位于靠近发射极的一侧，或者它可以位于发射极的相对侧附近。 然而，在所有实施例中，低K层不干扰双极晶体管的正常功能，并且基本上减小了通常与常规双极晶体管相关联的发射极 - 基极电容。

公开(公告)号：US06395611B1

公开(公告)日：2002-05-28

申请号：US09432725

申请日：1999-11-01

申请人： Nathan Belk ,  William Thomas Cochran ,  Michel Ranjit Frei ,  David Clayton Goldthorp ,  Shahriar Moinian ,  Kwok K. Ng ,  Mark Richard Pinto ,  Ya-Hong Xie

发明人： Nathan Belk ,  William Thomas Cochran ,  Michel Ranjit Frei ,  David Clayton Goldthorp ,  Shahriar Moinian ,  Kwok K. Ng ,  Mark Richard Pinto ,  Ya-Hong Xie

IPC分类号： H01L2120

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L23/645 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.

摘要翻译： 一种具有埋层的集成电路，用于增加形成在集成电路中的电感器的Q。 衬底包括高掺杂掩埋保存装置和闭锁特性。 电感器还可以包括电感器中增加的厚度导电层以进一步增加Q.本发明还涉及一种低损耗互连。

公开(公告)号：US20120304140A1

公开(公告)日：2012-11-29

申请号：US13114834

申请日：2011-05-24

申请人： Shawn Boshart ,  Shahriar Moinian ,  Joshua Williams ,  Hong-ha Vuong

发明人： Shawn Boshart ,  Shahriar Moinian ,  Joshua Williams ,  Hong-ha Vuong

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5063 ,  G06F2217/66

摘要： A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.

摘要翻译： 可参数化的设计系统与半导体模拟电路一起使用，并且包括被连接以提供对系统的访问的接口单元，连接到用于为设计实体提供可参数化的模拟构建块的库的数据库单元，以及连接以选择一个 参数为可参数化的模拟构建块之一，以满足设计实体的设计规范。 此外，可参数化设计系统还可以包括连接以模拟使用参数的设计实体的操作的模拟单元，以及连接以基于设计规范分析设计实体的参数的灵敏度的分析器单元。 还包括设计半导体模拟电路的方法。