公开(公告)号：US08399158B2

公开(公告)日：2013-03-19

申请号：US12977903

申请日：2010-12-23

Applicant: Chang Ju Choi ,  Cheng-Hsin Ma ,  Sven Henrichs ,  Robert H. Olshausen ,  Yulia Korobko

Inventor： Chang Ju Choi ,  Cheng-Hsin Ma ,  Sven Henrichs ,  Robert H. Olshausen ,  Yulia Korobko

IPC: G03F1/26

CPC classification number: G03F1/26 ,  G03F1/28

Abstract: Techniques are disclosed for fabricating lithography masks, which include a first level process comprising lithography and etching to form mask frame and in-die areas, and a second level process comprising lithography and etching to form one or more mask features in the in-die area. At least one of the mask features has a smallest dimension in the nanometer range (e.g., 32 nm technology node, or smaller). The techniques may be embodied, for example, in a lithography mask for fabricating semiconductor circuits. In one such example case, the mask includes a frame area and an in-die area formed after the frame area. The in-die area includes one or more mask features, at least one of which has a smallest dimension of less than 100 nm. The mask has a critical dimension bias of less than 20 nm and a structure that comprises a substrate and an absorber layer.

Abstract translation: 公开了用于制造光刻掩模的技术，其包括包括光刻和蚀刻以形成掩模框架和管芯内区域的第一级工艺，以及包括光刻和蚀刻以在管芯内区域形成一个或多个掩模特征的第二级工艺 。 掩模特征中的至少一个具有纳米范围内的最小尺寸（例如，32nm技术节点或更小）。 这些技术可以例如在用于制造半导体电路的光刻掩模中实现。 在一个这样的示例的情况下，掩模包括帧区域和在帧区域之后形成的管芯区域。 管芯内区域包括一个或多个掩模特征，其中至少一个具有小于100nm的最小尺寸。 掩模具有小于20nm的临界尺寸偏差和包括基底和吸收层的结构。

公开(公告)号：US20120164563A1

公开(公告)日：2012-06-28

申请号：US12977903

申请日：2010-12-23

Applicant: Chang Ju Choi ,  Cheng-Hsin Ma ,  Sven Henrichs ,  Robert H. Olshausen ,  Yulia Korobko

Inventor： Chang Ju Choi ,  Cheng-Hsin Ma ,  Sven Henrichs ,  Robert H. Olshausen ,  Yulia Korobko

IPC: G03F1/00

CPC classification number: G03F1/26 ,  G03F1/28

Abstract: Techniques are disclosed for fabricating lithography masks, which include a first level process comprising lithography and etching to form mask frame and in-die areas, and a second level process comprising lithography and etching to form one or more mask features in the in-die area. At least one of the mask features has a smallest dimension in the nanometer range (e.g., 32 nm technology node, or smaller). The techniques may be embodied, for example, in a lithography mask for fabricating semiconductor circuits. In one such example case, the mask includes a frame area and an in-die area formed after the frame area. The in-die area includes one or more mask features, at least one of which has a smallest dimension of less than 100 nm. The mask has a critical dimension bias of less than 20 nm and a structure that comprises a substrate and an absorber layer.

Abstract translation: 公开了用于制造光刻掩模的技术，其包括包括光刻和蚀刻以形成掩模框架和管芯内区域的第一级工艺，以及包括光刻和蚀刻以在管芯内区域形成一个或多个掩模特征的第二级工艺 。 掩模特征中的至少一个具有纳米范围内的最小尺寸（例如，32nm技术节点或更小）。 这些技术可以例如在用于制造半导体电路的光刻掩模中实现。 在一个这样的示例的情况下，掩模包括帧区域和在帧区域之后形成的管芯区域。 管芯内区域包括一个或多个掩模特征，其中至少一个具有小于100nm的最小尺寸。 掩模具有小于20nm的临界尺寸偏差和包括基底和吸收层的结构。

公开(公告)号：US20090001057A1

公开(公告)日：2009-01-01

申请号：US11824503

申请日：2007-06-29

Applicant: Cheng-Hsin Ma ,  Jeff J. Xu

Inventor： Cheng-Hsin Ma ,  Jeff J. Xu

IPC: B23K10/00

CPC classification number: H01L21/67253 ,  H01L21/67069 ,  H01L22/12

Abstract: In one embodiment, a system to measure changes and a dual damascene trench depth, comprises a power source, and impedance matching network coupled to the power source and to an electrode, a radio frequency sensor coupled to the impedance matching network, and a controller to establish a baseline correlation between a plasma impedance and the dual damascene trench depth, and use the baseline correlation to measure changes in the dual damascene trench depth.

Abstract translation: 在一个实施例中，测量变化和双镶嵌沟槽深度的系统包括耦合到电源和电极的电源和阻抗匹配网络，耦合到阻抗匹配网络的射频传感器，以及控制器 建立等离子体阻抗与双镶嵌槽深度之间的基线相关性，并使用基线相关度来测量双镶嵌槽深度的变化。

公开(公告)号：US20110159411A1

公开(公告)日：2011-06-30

申请号：US12655460

申请日：2009-12-30

Applicant: Bennett Olson ,  Max Lau ,  Cheng-hsin Ma ,  Jian Ma ,  Andrew T. Jamieson

Inventor： Bennett Olson ,  Max Lau ,  Cheng-hsin Ma ,  Jian Ma ,  Andrew T. Jamieson

IPC: G03F1/00 ,  G03F7/20

CPC classification number: G03F1/29 ,  G03F1/26 ,  G03F1/30 ,  G03F1/58

Abstract: A phase shift photomask blank has a quartz substrate, a lower chrome layer, a light-absorbing MoSi layer, and an upper chrome layer. This mask can be patterned in various ways to form a patterned photomask with both phase shift and binary areas.

Abstract translation: 相移光掩模坯料具有石英基板，下铬层，吸光MoSi层和上铬层。 该掩模可以以各种方式图案化以形成具有相移和二进制区域的图案化光掩模。