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    Mechanism for screening commands issued over a communications bus for selective execution by a processor
    1.
    发明授权
    Mechanism for screening commands issued over a communications bus for selective execution by a processor 失效
    用于筛选通过通信总线发出的用于由处理器选择性执行的命令的机制

    公开(公告)号：US5652837A

    公开(公告)日：1997-07-29

    申请号：US543228

    申请日：1995-10-13

    申请人： Nicholas Allen Warchol ,  Chester Pawlowski

    发明人： Nicholas Allen Warchol ,  Chester Pawlowski

    IPC分类号： G06F13/40 ,  G06F13/20

    CPC分类号： G06F13/4027

    摘要： The invention provides a new process and apparatus for generating and selectively processing command requests issued over a bus. Command requests are generated by devices, each of which may be authorized or not authorized to cause the execution of the requested command. A unique identifier is provided for each device. The command requests are received and the identity of the device which issued the command request is determined. The command is then executed only if the unique identifier associated with the requesting device indicates that the device is authorized to cause the execution of the requested command.

    摘要翻译： 本发明提供了一种用于生成和选择性地处理通过总线发出的命令请求的新的过程和装置。 命令请求由设备生成，每个设备可能被授权或未经授权才能执行所请求的命令。 为每个设备提供唯一的标识符。 接收到命令请求，并确定发出命令请求的设备的身份。 只有当与请求设备相关联的唯一标识符指示该设备被授权导致所请求的命令的执行时，才执行该命令。

    Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor
    2.
    发明授权
    Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor 失效
    用于采用提交信号和预取以在高性能I / O处理器中维持参考间排序的方法和装置

    公开(公告)号：US6085263A

    公开(公告)日：2000-07-04

    申请号：US956861

    申请日：1997-10-24

    申请人： Madhumitra Sharma ,  Chester Pawlowski ,  Kourosh Gharachorloo ,  Stephen R. Van Doren ,  Simon C. Steely, Jr.

    发明人： Madhumitra Sharma ,  Chester Pawlowski ,  Kourosh Gharachorloo ,  Stephen R. Van Doren ,  Simon C. Steely, Jr.

    IPC分类号： G06F12/08 ,  G06F13/12 ,  G06F13/14

    CPC分类号： G06F12/082 ,  G06F13/124 ,  G06F12/0862 ,  G06F2212/621

    摘要： An improved I/O processor (IOP) delivers high I/O performance while maintaining inter-reference ordering among memory reference operations issued by an I/O device as specified by a consistency model in a shared memory multiprocessor system. The IOP comprises a retire controller which imposes inter-reference ordering among the operations based on receipt of a commit signal for each operation, wherein the commit signal for a memory reference operation indicates the apparent completion of the operation rather than actual completion of the operation. In addition, the IOP comprises a prefetch controller coupled to an I/O cache for prefetching data into cache without any ordering constraints (or out-of-order). The ordered retirement functions of the IOP are separated from its prefetching operations, which enables the latter operations to be performed in an arbitrary manner so as to improve the overall performance of the system.

    摘要翻译： 改进的I / O处理器（IOP）提供高I / O性能，同时在由共享存储器多处理器系统中的一致性模型指定的I / O设备发出的存储器参考操作之间保持参考间排序。 IOP包括退出控制器，其基于对每个操作的提交信号的接收，在操作之间施加参考间排序，其中用于存储器参考操作的提交信号指示操作的明显完成，而不是实际完成操作。 此外，IOP包括耦合到I / O缓存的预取控制器，用于将数据预取到高速缓存中，而没有任何排序限制（或无序）。 IOP的有序退休功能与其预取操作分离，这使得后面的操作能够以任意方式执行，从而提高系统的整体性能。