公开(公告)号：US08603844B2

公开(公告)日：2013-12-10

申请号：US13454088

申请日：2012-04-24

申请人： Chi-Ming Chiou ,  Yu-Tsung Lee ,  Chin-Tzu Kao

发明人： Chi-Ming Chiou ,  Yu-Tsung Lee ,  Chin-Tzu Kao

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/124 ,  H01L29/66742 ,  H01L29/66765

摘要： A method for manufacturing a pixel structure is provided. A thin film transistor is formed on a substrate and an insulating layer is formed to cover the substrate and the thin film transistor. The insulating layer is patterned by a half-tone mask to form a protruding pattern, a sunken pattern connecting the protruding pattern, and a contact window inside the sunken pattern. A transparent conductive layer is formed to cover the protruding pattern and the sunken pattern, and filled in the contact window. A passivation layer is formed to cover the transparent conductive layer. A pixel electrode pattern is formed from the transparent conductive layer by removing a part of the passivation layer located on the protruding pattern, a part of the transparent conductive layer on the protruding pattern, and a part of the passivation layer located within the contact window. A pixel structure manufactured by the method is provided.

摘要翻译： 提供了一种用于制造像素结构的方法。 在基板上形成薄膜晶体管，形成绝缘层以覆盖基板和薄膜晶体管。 通过半色调掩模对绝缘层进行图案化以形成突出图案，连接突出图案的凹陷图案和凹陷图案内的接触窗口。 形成透明导电层以覆盖突出图案和凹陷图案，并填充在接触窗中。 形成钝化层以覆盖透明导电层。 通过去除位于突出图案上的钝化层的一部分，突出图案上的透明导电层的一部分和位于接触窗内部的钝化层的一部分，由透明导电层形成像素电极图案。 提供了通过该方法制造的像素结构。

公开(公告)号：US20120007628A1

公开(公告)日：2012-01-12

申请号：US12958346

申请日：2010-12-01

申请人： Chi-Ming Chiou

发明人： Chi-Ming Chiou

IPC分类号： G01R31/26

CPC分类号： G01R31/26 ,  G09G3/006 ,  G09G3/3648

摘要： A method for checking alignment accuracy of a thin film transistor includes providing a substrate, forming a first conductive layer on the substrate, performing a first patterning process to form a gate electrode of a thin film transistor and a first terminal and a second terminal of a testing device, forming a first insulating layer covering the first terminal, the second terminal and the gate electrode on the substrate, forming a contact hole substantially corresponding to the first terminal and the second terminal in the first insulating layer, forming a pixel electrode and a connecting electrode of the testing device in the first contact hole, and performing a close/open circuit test. When the first terminal, the connecting electrode and the second terminal construct a close circuit, alignment accuracy is confirmed. When the first terminal, the connecting electrode and the second terminal construct an open circuit, alignment inaccuracy is confirmed.

摘要翻译： 一种用于检查薄膜晶体管的对准精度的方法，包括提供衬底，在衬底上形成第一导电层，执行第一图案化工艺以形成薄膜晶体管的栅电极，以及第一端和第二端 在所述基板上形成覆盖所述第一端子，所述第二端子和所述栅电极的第一绝缘层，在所述第一绝缘层中形成与所述第一端子和所述第二端子大致对应的接触孔，形成像素电极和 在第一接触孔中的测试装置的连接电极，并执行闭合/断路测试。 当第一端子，连接电极和第二端子构成闭合电路时，确认对准精度。 当第一端子，连接电极和第二端子构成开路时，确认对准不精确。

公开(公告)号：US08581615B2

公开(公告)日：2013-11-12

申请号：US12958346

申请日：2010-12-01

申请人： Chi-Ming Chiou

发明人： Chi-Ming Chiou

IPC分类号： G01R31/26

CPC分类号： G01R31/26 ,  G09G3/006 ,  G09G3/3648

摘要： A method for checking alignment accuracy of a thin film transistor includes providing a substrate, forming a first conductive layer on the substrate, performing a first patterning process to form a gate electrode of a thin film transistor and a first terminal and a second terminal of a testing device, forming a first insulating layer covering the first terminal, the second terminal and the gate electrode on the substrate, forming a contact hole substantially corresponding to the first terminal and the second terminal in the first insulating layer, forming a pixel electrode and a connecting electrode of the testing device in the first contact hole, and performing a close/open circuit test. When the first terminal, the connecting electrode and the second terminal construct a close circuit, alignment accuracy is confirmed. When the first terminal, the connecting electrode and the second terminal construct an open circuit, alignment inaccuracy is confirmed.

摘要翻译： 一种用于检查薄膜晶体管的对准精度的方法，包括提供衬底，在衬底上形成第一导电层，执行第一图案化工艺以形成薄膜晶体管的栅电极，以及第一端和第二端 在所述基板上形成覆盖所述第一端子，所述第二端子和所述栅电极的第一绝缘层，在所述第一绝缘层中形成与所述第一端子和所述第二端子大致相对应的接触孔，形成像素电极和 在第一接触孔中的测试装置的连接电极，并执行闭合/断路测试。 当第一端子，连接电极和第二端子构成闭合电路时，确认对准精度。 当第一端子，连接电极和第二端子构成开路时，确认对准不精确。

公开(公告)号：US20130175532A1

公开(公告)日：2013-07-11

申请号：US13454088

申请日：2012-04-24

申请人： Chi-Ming Chiou ,  Yu-Tsung Lee ,  Chin-Tzu Kao

发明人： Chi-Ming Chiou ,  Yu-Tsung Lee ,  Chin-Tzu Kao

IPC分类号： H01L29/786 ,  H01L21/02

CPC分类号： H01L27/1288 ,  H01L27/124 ,  H01L29/66742 ,  H01L29/66765

摘要： A method for manufacturing a pixel structure is provided. A thin film transistor is formed on a substrate and an insulating layer is formed to cover the substrate and the thin film transistor. The insulating layer is patterned by a half-tone mask to form a protruding pattern, a sunken pattern connecting the protruding pattern, and a contact window inside the sunken pattern. A transparent conductive layer is formed to cover the protruding pattern and the sunken pattern, and filled in the contact window. A passivation layer is formed to cover the transparent conductive layer. A pixel electrode pattern is formed from the transparent conductive layer by removing a part of the passivation layer located on the protruding pattern, a part of the transparent conductive layer on the protruding pattern, and a part of the passivation layer located within the contact window. A pixel structure manufactured by the method is provided.

摘要翻译： 提供了一种用于制造像素结构的方法。 在基板上形成薄膜晶体管，形成绝缘层以覆盖基板和薄膜晶体管。 通过半色调掩模对绝缘层进行图案化以形成突出图案，连接突出图案的凹陷图案和凹陷图案内的接触窗口。 形成透明导电层以覆盖突出图案和凹陷图案，并填充在接触窗中。 形成钝化层以覆盖透明导电层。 通过去除位于突出图案上的钝化层的一部分，突出图案上的透明导电层的一部分和位于接触窗内部的钝化层的一部分，由透明导电层形成像素电极图案。 提供了通过该方法制造的像素结构。