公开(公告)号：US5512495A

公开(公告)日：1996-04-30

申请号：US390269

申请日：1995-02-16

申请人： Chia-Cu P. Mei ,  Satwinder Malhi

发明人： Chia-Cu P. Mei ,  Satwinder Malhi

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/266

CPC分类号： H01L29/66659 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/7835 ,  Y10S148/126

摘要： A high voltage PMOS transistor 7 has improved on resistance by adjusting impurity concentration in a lightly doped drift region rim 48 to compensate for impurity segregation which occurs during the growth phase of a thick field oxide 43. During fabrication of high voltage PMOS device 7, a shallow vertical junction 230 formed by impurity segregation into field oxide 43. Implanting an HV drift region p-tank rim adjustment 220 and annealing it forms a lateral junction 250 and isolates the shallow junction 230 under field oxide 43. Thereby, the on-resistance of high voltage PMOS transistor 7 is minimized.

摘要翻译： 高电压PMOS晶体管7通过调整轻掺杂漂移区边缘48中的杂质浓度来改善导通电阻，以补偿在厚场氧化物43的生长阶段期间发生的杂质偏析。在制造高电压PMOS器件7期间， 通过杂质偏析形成场氧化物43形成的浅垂直结230.注入HV漂移区域p型槽边缘调节件220并进行退火形成横向接合部250，并将浅结230隔离在场氧化物43下。由此，导通电阻 高电压PMOS晶体管7最小化。

公开(公告)号：US5501994A

公开(公告)日：1996-03-26

申请号：US487763

申请日：1995-06-07

申请人： Chia-Cu P. Mei

发明人： Chia-Cu P. Mei

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L21/265

CPC分类号： H01L27/088 ,  H01L27/0922

摘要： An integrated circuit containing high voltage PMOS and/or NMOS devices as well as low voltage PMOS and/or NMOS devices and a simple low cost method for making same that is adaptable to many types of semiconductor processes; furthermore, the breakdown voltage of the high voltage devices is easily adjusted so that the value of R.sub.on can be optimized. High voltage MOS devices 6 and 7 are formed on substrate 10 using essentially the same process steps as are used to form low voltage MOS devices 8 and 9. Low values of R.sub.on are obtained by selecting impurity concentration levels for HV drift region n-tank 21 and for HV drift region p-tank 41 so that the depletion region distance D1 bounded by equipotential lines 301a and 301j and the depletion region distance D1a bounded by equipotential lines 401a and 401h are smaller than the physical size D2 and D2a of drift regions 41 and 21, respectively.

摘要翻译： 包含高电压PMOS和/或NMOS器件以及低电压PMOS和/或NMOS器件的集成电路和用于制造适合于许多类型的半导体工艺的简单的低成本方法; 此外，容易调整高压器件的击穿电压，使得可以优化Ron的值。 使用与用于形成低电压MOS器件8和9的基本相同的工艺步骤，在衬底10上形成高电压MOS器件6和7.通过选择HV漂移区域n槽21的杂质浓度水平来获得低的Ron值 并且对于HV漂移区域p型槽41，使得由等势线301a和301j限定的耗尽区域距离D1和由等电位线401a和401h限定的耗尽区域距离D1a小于漂移区域41的物理尺寸D2和D2a 21。

公开(公告)号：US5548147A

公开(公告)日：1996-08-20

申请号：US369973

申请日：1995-01-05

申请人： Chia-Cu P. Mei

发明人： Chia-Cu P. Mei

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/76 ,  H01L21/265

CPC分类号： H01L29/7835 ,  H01L29/66659 ,  H01L29/7801

摘要： A high voltage PMOS or NMOS transistor 7 has improved on-resistance by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise. By shortening the physical distance d2 between drain 42 and channel region 49, the drain to source on-resistance of the high voltage device is reduced and the performance of high voltage device 7 is thereby improved.

公开(公告)号：US5498554A

公开(公告)日：1996-03-12

申请号：US224948

申请日：1994-04-08

申请人： Chia-Cu P. Mei

发明人： Chia-Cu P. Mei

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

CPC分类号： H01L27/088 ,  H01L27/0922

摘要： An integrated circuit containing high voltage PMOS and/or NMOS devices as well as low voltage PMOS and/or NMOS devices and a simple low cost method for making same that is adaptable to many types of semiconductor processes; furthermore, the breakdown voltage of the high voltage devices is easily adjusted so that the value of R.sub.on can be optimized. High voltage MOS devices 6 and 7 are formed on substrate 10 using essentially the same process steps as are used to form low voltage MOS devices 8 and 9. Low values of R.sub.on are obtained by selecting impurity concentration levels for HV drift region n-tank 21 and for HV drift region p-tank 41 so that the depletion region distance D1 bounded by equipotential lines 301a and 301j and the depletion region distance D1a bounded by equipotential lines 401a and 401h are smaller than the physical size D2 and D2a of drift regions 41 and 21, respectively.

摘要翻译： 包含高电压PMOS和/或NMOS器件以及低电压PMOS和/或NMOS器件的集成电路和用于制造适合于许多类型的半导体工艺的简单的低成本方法; 此外，容易调整高压器件的击穿电压，使得可以优化Ron的值。 使用与用于形成低电压MOS器件8和9的基本相同的工艺步骤，在衬底10上形成高电压MOS器件6和7.通过选择HV漂移区域n槽21的杂质浓度水平来获得低的Ron值 并且对于HV漂移区域p型槽41，使得由等势线301a和301j限定的耗尽区域距离D1和由等电位线401a和401h限定的耗尽区域距离D1a小于漂移区域41的物理尺寸D2和D2a 21。

公开(公告)号：US5585660A

公开(公告)日：1996-12-17

申请号：US482065

申请日：1995-06-07

申请人： Chia-Cu P. Mei

发明人： Chia-Cu P. Mei

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7835 ,  H01L29/66659 ,  H01L29/7801

摘要： A high voltage PMOS or NMOS transistor 7 has improved on-resistance by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise. By shortening the physical distance d2 between drain 42 and channel region 49, the drain to source on-resistance of the high voltage device is reduced and the performance of high voltage device 7 is thereby improved.

摘要翻译： 高电压PMOS或NMOS晶体管7通过截断栅极场氧化物43具有改善的导通电阻，使得漏极区42可能被注入更接近沟道区49。 通过缩短漏极42和沟道区域49之间的物理距离d2，降低了高压器件的漏极/漏极导通电阻，从而提高了高压器件7的性能。