公开(公告)号：US07860120B1

公开(公告)日：2010-12-28

申请号：US09916715

申请日：2001-07-27

申请人： Chi-Lie Wang ,  Li-Jau Yang ,  Kap Soh ,  Chin-Li Mou

发明人： Chi-Lie Wang ,  Li-Jau Yang ,  Kap Soh ,  Chin-Li Mou

IPC分类号： H04L12/56

CPC分类号： H04L49/9052 ,  H04L47/6215 ,  H04L49/9005

摘要： A plurality of virtual paths in a network interface between a host port and a network port are managed according to respective priorities using dynamic buffer allocation. Thus, multiple levels of quality of service are supported through a single physical network port. Variant processes are applied for handling packets which have been downloaded to a network interface, prior to transmission onto the network. The network interface also includes memory used as a transmit buffer, that stores data packets received from the host computer on the first port, and provides data to the second port for transmission on the network. A control circuit in the network interface manages the memory as a plurality of first-in-first-out FIFO queues having respective priorities. Logic places a packet received from the host processor into one of the plurality of FIFO queues according to a quality of service parameter associated with the packets. Logic transmits the packets in the plurality of FIFO queues according to respective priorities. Logic dynamically allocates the memory using a list of buffer descriptors for corresponding buffers in said memory. The list of buffer descriptors comprises a free buffer list and a used buffer list for each of the virtual paths served by the system. A used buffer descriptor is released from the used buffer list, after the data stored in the corresponding used buffer has been transmitted, to the free buffer list for a virtual path which has the largest amount traffic or which has the smallest number of free buffers in its free buffer list.

摘要翻译： 在主机端口和网络端口之间的网络接口中的多个虚拟路径根据各自的优先级使用动态缓冲器分配进行管理。 因此，通过单个物理网络端口支持多级服务质量。 在传输到网络之前，应用变体过程来处理已经下载到网络接口的分组。 网络接口还包括用作发送缓冲器的存储器，其将从主计算机接收的数据分组存储在第一端口上，并且向第二端口提供数据以在网络上传输。 网络接口中的控制电路将存储器作为具有各自优先级的多个先进先出FIFO队列进行管理。 根据与分组相关联的服务质量参数，逻辑将从主机处理器接收到的分组放置在多个FIFO队列中的一个中。 逻辑根据各自的优先级传输多个FIFO队列中的分组。 逻辑使用所述存储器中的相应缓冲器的缓冲器描述符列表动态地分配存储器。 缓冲器描述符的列表包括由系统服务的每个虚拟路径的空闲缓冲器列表和使用的缓冲器列表。 在使用缓冲区列表中释放已使用的缓冲区描述符后，将存储在相应的已用缓冲区中的数据发送到具有最大数量流量或具有最小数量的可用缓冲区的虚拟路径的空闲缓冲区列表中 其免费缓冲列表。

公开(公告)号：US06970921B1

公开(公告)日：2005-11-29

申请号：US09916377

申请日：2001-07-27

申请人： Chi-Lie Wang ,  Li-Jau Yang ,  Kap Soh ,  Chin-Li Mou

发明人： Chi-Lie Wang ,  Li-Jau Yang ,  Kap Soh ,  Chin-Li Mou

IPC分类号： G06F15/177 ,  H04L29/06

CPC分类号： H04L47/10 ,  H04L47/2441 ,  H04L47/245 ,  H04L47/50 ,  H04L47/56 ,  H04L47/6215 ,  H04L47/6285 ,  H04L49/90 ,  H04L49/901 ,  H04L63/0272

摘要： A plurality of virtual paths in a network interface between a host port and a network port are managed according to respective priorities. Thus, multiple levels of quality of service are supported through a single physical network port. Variant processes are applied for handling packets which have been downloaded to a network interface, prior to transmission onto the network. The network interface also includes memory used as a transmit buffer, that stores data packets received from the host computer on the first port, and provides data to the second port for transmission on the network. A control circuit in the network interface manages the memory as a plurality of first-in-first-out FIFO queues having respective priorities. Logic places a packet received from the host processor into one of the plurality of FIFO queues according to a quality of service parameter associated with the packets. Logic transmits the packets in the plurality of FIFO queues according to respective priorities. The transmit packet buffer may be statically or dynamically allocated memory.

摘要翻译： 在主机端口和网络端口之间的网络接口中的多个虚拟路径根据各自的优先级进行管理。 因此，通过单个物理网络端口支持多级服务质量。 在传输到网络之前，应用变体过程来处理已经下载到网络接口的分组。 网络接口还包括用作发送缓冲器的存储器，其将从主计算机接收的数据分组存储在第一端口上，并且向第二端口提供数据以在网络上传输。 网络接口中的控制电路将存储器作为具有各自优先级的多个先进先出FIFO队列进行管理。 根据与分组相关联的服务质量参数，逻辑将从主机处理器接收到的分组放置在多个FIFO队列中的一个中。 逻辑根据各自的优先级传输多个FIFO队列中的分组。 发送分组缓冲器可以是静态或动态分配的存储器。

公开(公告)号：US06963921B1

公开(公告)日：2005-11-08

申请号：US09785015

申请日：2001-02-16

申请人： Li-Jau Yang ,  Chi-Lie Wang ,  Kap Soh ,  Chin-Li Mou

发明人： Li-Jau Yang ,  Chi-Lie Wang ,  Kap Soh ,  Chin-Li Mou

IPC分类号： G06F15/16 ,  H04L12/56 ,  H04L29/06

CPC分类号： H04L69/16 ,  H04L49/90 ,  H04L49/9094 ,  H04L69/12 ,  H04L69/161 ,  H04L69/163 ,  H04L69/166 ,  H04L69/22

摘要： A hardware packet accelerator parses incoming packets to retrieve header data for building a frame status and for verifying the incoming packets are part of an established connection with a host. The accelerator includes a connection database that allows retrieval of connection information based on an index constructed from a hashed TCP connection address. The frame status comprises information needed to perform packet re-assembly and is stored in a memory that is local (directly accessible) by a processing device that performs the packet re-assembly. Among other advantages, the processing device does not need to read packet header data from a packet buffer, saving large amounts of header data retrieval time.

摘要翻译： 硬件分组加速器解析输入分组以检索用于构建帧状态的头部数据，并且用于验证传入的分组是与主机建立的连接的一部分。 加速器包括连接数据库，其允许基于由散列TCP连接地址构建的索引检索连接信息。 帧状态包括执行分组重组所需的信息，并且被存储在由执行分组重组的处理设备本地（可直接访问）的存储器中。 除了其他优点之外，处理设备不需要从分组缓冲器读取分组报头数据，从而节省大量的报头数据检索时间。