Abstract:
In one embodiment of the invention, an apparatus for authenticating a flash program is provided. The apparatus comprises a hardware unique key, a register storing a customer identity (ID) and a message authentication code (MAC) generation unit. The MAC generation unit acquires a root key corresponding to the hardware unique key and the customer ID, and generates a MAC for the flash program using the acquired root key, wherein the content of the register is locked to avoid modification of the stored customer ID until the next system reset.
Abstract:
An apparatus for performing timer management regarding a system timer scheduler service includes: a processor arranged to control operations of the apparatus; an ordinary timer arranged to provide the processor with time ticks, for use of timing control; and a hardware-based Operating System (OS) timer arranged to provide the processor with at least one scheduler timer, for use of the system timer scheduler service. An associated method for performing timer management regarding a system timer scheduler service is also provided, and can be applied to the apparatus. In particular, the apparatus and the method can give considerations to both run-time power consumption and sleep mode power consumption. For example, the hardware-based OS timer can support an event-based OS timer scheduler to save the run-time power consumption. In another example, the hardware-based OS timer can support timer alignment in accordance with modulator/demodulator (modem) activities to minimize the sleep mode power consumption.
Abstract:
An apparatus for capturing and storing real-time images is provided. A camera module records frames corresponding to sensed light, outputs pixel data of the frames on a data bus, and generates synchronization control signals to control the synchronized transmission of the frames. An interrupt controller receives the synchronization control signals and correspondingly generates interrupt signals. A processing unit receives the interrupt signals, fetches the pixel data of the frames on the data bus according to at least one of the interrupt signals, and stores the fetched pixel data in a memory device.
Abstract:
An apparatus for performing timer management regarding a system timer scheduler service includes: a processor arranged to control operations of the apparatus; an ordinary timer arranged to provide the processor with time ticks, for use of timing control; and a hardware-based Operating System (OS) timer arranged to provide the processor with at least one scheduler timer, for use of the system timer scheduler service. An associated method for performing timer management regarding a system timer scheduler service is also provided, and can be applied to the apparatus. In particular, the apparatus and the method can give considerations to both run-time power consumption and sleep mode power consumption. For example, the hardware-based OS timer can support an event-based OS timer scheduler to save the run-time power consumption. In another example, the hardware-based OS timer can support timer alignment in accordance with modulator/demodulator (modem) activities to minimize the sleep mode power consumption.
Abstract:
An apparatus for capturing and storing real-time images is provided. A camera module records frames corresponding to sensed light, outputs pixel data of the frames on a data bus, and generates synchronization control signals to control the synchronized transmission of the frames. An interrupt controller receives the synchronization control signals and correspondingly generates interrupt signals. A processing unit receives the interrupt signals, fetches the pixel data of the frames on the data bus according to at least one of the interrupt signals, and stores the fetched pixel data in a memory device.
Abstract:
A wireless apparatus, an integrated circuit, and a method thereof. The wireless apparatus, providing hardware security, comprises a secure memory and a secure Integrated Circuit (IC). The secure memory comprises security authentication data. The secure IC, coupled to the secured memory, comprises a processor, a security controller, a security pin, and a read only memory (ROM). The processor is configured to process data. The security controller, coupled to the processor and the secure memory, translates the security authentication data to the processor. The security pin, coupled to the security controller, enables security of the secure IC. The ROM, coupled to the processor, has stored thereon instructions determining a security level according to the security authentication data and the security of the secure IC. The instructions are executed by the processor upon a boot-up operation.