-
1.发明授权Technique for placement of pipelining stages in multi-stage datapath elements with an automated circuit design system 失效使用自动化电路设计系统在多级数据路径元件中放置流水线阶段的技术
公开(公告)号：US5133069A
公开(公告)日：1992-07-21
申请号：US297112
申请日：1989-01-13
CPC分类号： G06F17/10 , G06F17/5045 , G06F9/3869
摘要： According to a method for designating the locations of pipelining stages in multi-stage datapath elements, the delay associated with each stage of the multi-stage element is estimated. Then, beginning with a designated stage of the multi-stage element, the estimated delays for the individual stages are added to obtain an accumulated delay time. Whenever the accumulated delay time exceeds a desired cycle time, a pipelining stage is inserted into the multi-stage element prior to the stage which caused the accumulated delay time to exceed the desired operating cycle time. Then, the method is continued for succeeding stages in the datapath element until all of its stages have been accounted for.
摘要翻译： 根据用于指定多级数据通路元件中的流水线阶段的位置的方法，估计与多级元件的每个级相关联的延迟。 然后，从多级元件的指定级开始，加入各级的估计延迟，以获得累积的延迟时间。 每当积累的延迟时间超过期望的周期时间时，在阶段之前将流水线级插入到多级元件中，这导致累积的延迟时间超过期望的操作周期时间。 然后，该方法继续用于数据通路元件中的后续阶段，直到其所有阶段都被考虑为止。
-
公开(公告)号：US5126965A
公开(公告)日：1992-06-30
申请号：US696310
申请日：1991-04-29
CPC分类号： G06F7/507 , G06F17/5045 , G06F2207/4812
摘要： A conditional-sum carry structure has an architecture which is sufficiently regular that the structure can be conveniently generated by an automated compiler. The carry structure includes a column of input cells, each of the cells in the column being operative for receiving binary numbers and, for each of the received numbers, generating a sum bit and two carry-out bits. Further the carry structure includes an array of columns of binary logic elements comprised of dual multiplexers (MUX MUX elements), dual exclusive OR gates (XOR XOR elements), multiplexer and exclusive OR gate circuits (MUX XOR elements) and multiplexer units (ONE MUX elements) for receiving sum bits and carry-out bits from the input cells and for performing the operations of a conditional-sum carry structure.
摘要翻译： 条件和进位结构具有足够规则的结构，可以通过自动编译器方便地生成结构。 进位结构包括一列输入单元，该列中的每个单元可操作用于接收二进制数，并且对于每个接收的数字，产生和位和两个进位位。 进一步，进位结构包括由双重复用器（MUX MUX元件），双异或门（XOR XOR元件），多路复用器和异或门电路（MUX XOR元件）和多路复用器单元（ONE MUX）组成的二进制逻辑元件列列 元件），用于从输入单元接收和位和执行位，并用于执行条件和进位结构的操作。
-
公开(公告)号：US5297069A
公开(公告)日：1994-03-22
申请号：US929867
申请日：1992-08-13
CPC分类号： H03H17/06
摘要： Output data points of a digital FIR filter are calculated by storing input data points in an addressable memory and accessing the addressable memory to supply a new input data point exactly once for each output data point after a first output data point and storing each input data point in a first recirculating memory for so long as that input data point is needed to calculate a next output data point. The input data points stored in the first recirculating memory are used to calculate output data points. Furthermore, coefficients are stored in a second recirculating memory and are used to calculate the output data points. As a result, only one memory access is required per output data point.
摘要翻译： 通过将输入数据点存储在可寻址存储器中并访问可寻址存储器以在第一输出数据点之后为每个输出数据点提供一次新的输入数据点并存储每个输入数据点来计算数字FIR滤波器的输出数据点 在第一再循环存储器中，只要需要输入数据点来计算下一个输出数据点。 存储在第一再循环存储器中的输入数据点用于计算输出数据点。 此外，系数存储在第二再循环存储器中，并用于计算输出数据点。 因此，每个输出数据点只需要一个存储器访问。
-
公开(公告)号：US5291457A
公开(公告)日：1994-03-01
申请号：US839192
申请日：1992-02-20
CPC分类号： H03K3/78
摘要： A sequentially accessible, non-volatile data storage circuit for generating constants includes a logic array for non-volatile storage of programmed data words and a recirculating shift register for causing the first one of the data words to appear at a data output of the data storage circuit in response to a reset signal and to cause the next data word to appear at the data output in response to a clock signal.
摘要翻译： 用于产生常数的可顺序访问的非易失性数据存储电路包括用于非易失性存储编程数据字的逻辑阵列和用于使第一数据字出现在数据存储器的数据输出端的再循环移位寄存器 响应于复位信号，并且响应于时钟信号使下一个数据字出现在数据输出端。
-
5.发明授权Automated method of inserting pipeline stages in a data path element to achieve a specified operating frequency 失效在数据路径元素中插入流水线级以实现指定的工作频率的自动化方法
公开(公告)号：US5212782A
公开(公告)日：1993-05-18
申请号：US680004
申请日：1991-04-01
CPC分类号： G06F9/3869 , G06F17/5045 , G06F7/00
摘要： According to a technique for determining delays through multi-stage datapath elements, estimates of the delays through each stage of the datapath element are computed in accordance with an the equation such as:D.sub.s =D.sub.b N.sub.b +Cwhere D.sub.s is the estimated stage delay, D.sub.b is a delay associated with communication between bits in the stage, N.sub.b is the number of bits in the datapath element, and C is a constant. The estimated stage delays are used to determine positions of pipelining stages in the datapath element.
摘要翻译： 根据用于通过多级数据通路元件确定延迟的技术，根据以下等式计算对数据通路元件的每个级的延迟的估计：Ds = DbNb + C其中Ds是估计级延迟，Db 是与阶段中的位之间的通信相关联的延迟，Nb是数据路径元素中的位数，C是常数。 估计的阶段延迟用于确定数据路径元素中流水线阶段的位置。
-
-
-
-
搜索结果
5 条记录 (耗时 0.01 秒)
