公开(公告)号：US20080062806A1

公开(公告)日：2008-03-13

申请号：US11850510

申请日：2007-09-05

Applicant: Christophe Rodat ,  Thierry Giovinazzi

Inventor： Christophe Rodat ,  Thierry Giovinazzi

IPC: G11C8/12

CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2207/002 ,  G11C2213/79

Abstract: An integrated circuit includes a non-volatile memory having memory cells, a memory cell selection circuit having selection blocks, a first device supplying a first voltage applicable to memory cells, a second device supplying a second voltage applicable to memory cells. Each memory cell selection block includes a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device. The first sub-block includes MOS transistors of a first type of conductivity, and the second sub-block includes MOS transistors of a second type of conductivity. Application may be particularly but not exclusively to phase change memories.

Abstract translation: 集成电路包括具有存储单元的非易失性存储器，具有选择块的存储单元选择电路，提供适用于存储单元的第一电压的第一器件，提供适用于存储器单元的第二电压的第二器件。 每个存储器单元选择块包括用于将存储器单元链接到第一设备的第一选择子块和将存储器单元链接到第二设备的第二选择子块。 第一子块包括具有第一类导电性的MOS晶体管，第二子块包括第二导电类型的MOS晶体管。 应用可以特别地但不是排他地用于相变存储器。

公开(公告)号：US07599218B2

公开(公告)日：2009-10-06

申请号：US11850510

申请日：2007-09-05

Applicant: Christophe Rodat ,  Thierry Giovinazzi

Inventor： Christophe Rodat ,  Thierry Giovinazzi

IPC: G11C16/04

CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2207/002 ,  G11C2213/79

Abstract: An integrated circuit includes a non-volatile memory having memory cells, a memory cell selection circuit having selection blocks, a first device supplying a first voltage applicable to memory cells, a second device supplying a second voltage applicable to memory cells. Each memory cell selection block includes a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device. The first sub-block includes MOS transistors of a first type of conductivity, and the second sub-block includes MOS transistors of a second type of conductivity. Application may be particularly but not exclusively to phase change memories.

Abstract translation: 集成电路包括具有存储单元的非易失性存储器，具有选择块的存储单元选择电路，提供适用于存储单元的第一电压的第一器件，提供适用于存储器单元的第二电压的第二器件。 每个存储器单元选择块包括用于将存储器单元链接到第一设备的第一选择子块和将存储器单元链接到第二设备的第二选择子块。 第一子块包括具有第一类导电性的MOS晶体管，第二子块包括第二导电类型的MOS晶体管。 应用可以特别地但不排他地用于相变存储器。