SYSTEMS AND METHODS FOR EFFICIENT SLURRY APPLICATION FOR CHEMICAL MECHANICAL POLISHING
    1.
    发明申请
    SYSTEMS AND METHODS FOR EFFICIENT SLURRY APPLICATION FOR CHEMICAL MECHANICAL POLISHING 审中-公开
    用于化学机械抛光的有效浆料的系统和方法

    公开(公告)号:US20080220698A1

    公开(公告)日:2008-09-11

    申请号:US11683142

    申请日:2007-03-07

    IPC分类号: B24C1/00

    CPC分类号: B24B37/04 B24B57/02

    摘要: An embodiment relates generally to a chemical mechanical polishing apparatus. The apparatus includes a platen adapted to receive a wafer to be chemical-mechanically polished and a polishing pad configured to polish the wafer. The apparatus also includes a slurry feed line configured to provide slurry to the polishing pad and at least one slurry dispensing outlet coupled to the slurry feed line and configured to dispense slurry as a mist of small droplets ranging from submicron to about 500 microns.

    摘要翻译: 实施例一般涉及化学机械抛光装置。 该设备包括适于接收待化学机械抛光的晶片的台板和被配置为抛光晶片的抛光垫。 该设备还包括浆料供给管线,其被配置为向抛光垫提供浆料,以及至少一个浆料分配出口,其连接到浆料进料管线并且被配置为以小亚微米至约500微米的小液滴的雾分配浆料。

    Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity
    2.
    发明授权
    Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity 有权
    具有布线层填充结构的方法和半导体器件以改善平坦化均匀性

    公开(公告)号:US06693357B1

    公开(公告)日:2004-02-17

    申请号:US10388042

    申请日:2003-03-13

    IPC分类号: H01L2348

    摘要: Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during metalization processing. One approach employs fill structures of varying sizes where smaller fill structures are formed near wiring regions having high aspect ratio wiring structures and larger fill structures are located near wiring regions with lower aspect ratio wiring structures. Another approach provides fill structures with varying amounts of openings, with fill structures having few or no openings being provided near low aspect ratio wiring structures and fill structures having more openings being located near higher aspect ratio wiring structures.

    摘要翻译: 公开了半导体器件及其制造方法,其中在导电布线结构之间的互连布线层中的填充区域中提供导电填充结构,以促进金属化处理期间的平坦化均匀性。 一种方法采用不同尺寸的填充结构,其中在具有高纵横比布线结构的布线区域附近形成较小的填充结构,并且较大的填充结构位于具有较低纵横比布线结构的布线区附近。 另一种方法提供具有不同数量的开口的填充结构,其中填充结构在低纵横比布线结构附近提供很少的或没有开口,并且具有更多开口的填充结构位于较高纵横比布线结构附近。

    Dummy Contact Fill to Improve Post Contact Chemical Mechanical Polish Topography
    3.
    发明申请
    Dummy Contact Fill to Improve Post Contact Chemical Mechanical Polish Topography 审中-公开
    化学机械抛光地形

    公开(公告)号:US20090087956A1

    公开(公告)日:2009-04-02

    申请号:US11862668

    申请日:2007-09-27

    IPC分类号: H01L21/8238 H01L21/4763

    摘要: State of the art Integrated Circuits (ICs) encompass a variety of circuits, which have a wide variety of contact densities as measured in regions from 10 to 1000 microns in size. Fabrication processes for contacts have difficulty with high and low contact densities on the same IC, leading to a high incidence of electrical shorts and reduced operating speed of the circuits. This problem is expected to worsen as feature sizes shrink in future technology nodes. This invention is an electrically non-functional contact, known as a dummy contact, that is utilized to attain a more uniform distribution of contacts across an IC, which allows contact fabrication processes to produce ICs with fewer defects, and a method for forming said dummy contacts in ICs.

    摘要翻译: 最先进的集成电路(IC)包括各种电路,其具有在10至1000微米尺寸的区域中测量的各种接触密度。 触点的制造过程在同一个IC上具有高和低接触密度的困难,导致电短路的高发生率和电路的降低的操作速度。 随着未来技术节点的特征尺寸缩小,这个问题预计会恶化。 本发明是被称为虚拟接触件的电非功能性接触件,其用于实现跨越IC的更均匀的接触分布,这允许接触制造工艺制造具有较少缺陷的IC,以及用于形成所述虚拟器件的方法 IC中的联系人

    Post-polish treatment for inhibiting copper corrosion
    4.
    发明授权
    Post-polish treatment for inhibiting copper corrosion 有权
    后腐蚀处理以抑制铜腐蚀

    公开(公告)号:US07268073B2

    公开(公告)日:2007-09-11

    申请号:US10985193

    申请日:2004-11-10

    IPC分类号: H01L21/44

    CPC分类号: H01L21/76886 H01L21/7684

    摘要: Methods (102) are presented for protecting copper structures (26) from corrosion in the fabrication of semiconductor devices (2), wherein a thin semiconductor or copper-semiconductor alloy corrosion protection layer (30) is formed on an exposed surface (26a) of a copper structure (26) prior to performance of metrology operations (206), so as to inhibit corrosion of the copper structure (26). All or a portion of the corrosion protection layer (30) is then removed (214) in forming an opening in an overlying dielectric (44) in a subsequent interconnect layer.

    摘要翻译: 在半导体器件(2)的制造中提出了用于保护铜结构(26)免受腐蚀的方法(102),其中在暴露表面(26a)上形成薄的半导体或铜 - 半导体合金腐蚀保护层(30) 在执行计量操作(206)之前,铜结构(26),以便抑制铜结构(26)的腐蚀。 然后在随后的互连层中在覆盖电介质(44)中形成开口的全部或一部分腐蚀保护层(30)被去除(214)。