公开(公告)号：US07566627B2

公开(公告)日：2009-07-28

申请号：US11771298

申请日：2007-06-29

Applicant: Phillip D Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

Inventor： Phillip D Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

IPC: H01L21/20

CPC classification number: H01L28/10 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.

Abstract translation: 根据本发明，具有气隙的电感器，半导体器件，集成电路及其制造方法。 制造具有气隙的电感器的方法可以包括在包括一个或多个电感器环路，一个或多个通孔以及一个或多个铜隔板结构的金属间介电层中制造第一级电感器，形成级间 电介质层，并且重复步骤以形成两个或更多级别的电感器。 该方法还可以包括形成提取通孔，通过使用超临界流体过程去除与金属介电层相连的部分金属介电层，从而在电感器环之间形成气隙，并形成非共形层以密封提取 通过。

公开(公告)号：US20080290515A1

公开(公告)日：2008-11-27

申请号：US11753926

申请日：2007-05-25

Applicant: Valli Arunachalam ,  Satyavolu Srinivas Papa Rao ,  Sanjeev Aggarwal ,  Stephen Grunow

Inventor： Valli Arunachalam ,  Satyavolu Srinivas Papa Rao ,  Sanjeev Aggarwal ,  Stephen Grunow

IPC: H01L23/522 ,  H01L21/31 ,  H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer.

Abstract translation: 根据本发明，存在扩散阻挡层，集成电路和半导体器件及其制造方法。 制造扩散阻挡层的方法可以包括提供电介质层，通过将电介质层暴露于含硅环境，在介电层上形成第一富硅层，并在第一富硅层上形成阻挡层。

公开(公告)号：US20080153393A1

公开(公告)日：2008-06-26

申请号：US11716804

申请日：2007-03-12

Applicant: Linlin Chen ,  Li Chen ,  Satyavolu Srinivas Papa Rao

Inventor： Linlin Chen ,  Li Chen ,  Satyavolu Srinivas Papa Rao

IPC: B24B1/00

CPC classification number: B24B37/042

Abstract: A method for serially polishing a plurality of semiconductor wafers, wherein a CMP apparatus having a first polishing pad and a second polishing pad is provided. A first slurry composition is disposed between the first polishing pad and a first wafer when the first wafer is in a first state, and a first polishing on the first wafer via the first polishing pad and first slurry composition is commenced at a first commencement time. A second slurry composition is disposed between the second polishing pad and a second wafer when the second wafer is in a second state, and a second polishing on the second wafer via the second polishing pad and second slurry is commenced at a second commencement time, wherein the second commencement time differs from the first commencement time by a first intermediate period. One or more of the first wafer and the second wafer is rinsed with a pre-rinse agent for at least a portion of the first intermediate period. The first polishing and second polishing are halted at substantially the same end time, therein placing the first wafer in the second state and the second wafer in a third state.

Abstract translation: 一种串联抛光多个半导体晶片的方法，其中提供了具有第一抛光垫和第二抛光垫的CMP装置。 当第一晶片处于第一状态时，第一浆料组合物设置在第一抛光垫和第一晶片之间，并且经由第一抛光垫和第一浆料组合物在第一晶片上的第一次抛光在第一次启动时开始。 当第二晶片处于第二状态时，第二浆料组合物设置在第二抛光垫和第二晶片之间，并且经由第二抛光垫和第二浆料在第二晶片上的第二抛光在第二次开始时间开始，其中 第二开始时间与第一开始时间不同于第一中间时段。 第一晶片和第二晶片中的一个或多个用预漂洗剂冲洗至少第一中间周期的一部分。 第一抛光和第二抛光在基本相同的结束时间停止，其中将第一晶片置于第二状态，而第二晶片处于第三状态。

公开(公告)号：US07212607B1

公开(公告)日：2007-05-01

申请号：US11346054

申请日：2006-02-02

Applicant: Satyavolu Srinivas Papa Rao ,  Richard L. Guldi ,  Basab Chatterjee

Inventor： Satyavolu Srinivas Papa Rao ,  Richard L. Guldi ,  Basab Chatterjee

IPC: G01B15/06

CPC classification number: G01N23/18

Abstract: An x-ray confocal defect detection system comprises an x-ray source, a confocal component, and defect detectors and operates on a target portion of a semiconductor device. The x-ray source generates x-ray energy. The semiconductor device includes a plurality of formed layers. The target portion is a selected layer or portion of the plurality of formed layers. At least a portion of the x-ray is transmitted through the semiconductor device as transmitted x-ray. The confocal component receives the transmitted x-ray and passes target x-ray intensity from the target portion of the transmitted x-ray energy. Detectors receive the target x-ray from the confocal component from which defect analysis can be performed.

Abstract translation: x射线共焦缺陷检测系统包括x射线源，共焦分量和缺陷检测器，并在半导体器件的目标部分上操作。 x射线源产生x射线能量。 半导体器件包括多个形成的层。 目标部分是所选择的层或多个成形层的一部分。 X射线的至少一部分透射通过半导体器件作为透射的x射线。 共聚焦组件接收透射的X射线，并从所传输的x射线能量的目标部分传递目标x射线强度。 检测器从可以进行缺陷分析的共聚焦组件接收目标X射线。

公开(公告)号：US08604587B2

公开(公告)日：2013-12-10

申请号：US12689685

申请日：2010-01-19

Applicant: Edmund Burke ,  Satyavolu Srinivas Papa Rao ,  Timothy Alan Rost

Inventor： Edmund Burke ,  Satyavolu Srinivas Papa Rao ,  Timothy Alan Rost

IPC: H01L21/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection cladding (109) for the copper metal (104b) of the top metal interconnect.

Abstract translation: 片上去耦电容器（106）及其制造方法。 去耦电容器（106）集成在顶部金属互连级（104）处，并且包括用于顶部金属互连的铜金属（104b）的表面保护包层（109）。

公开(公告)号：US08211794B2

公开(公告)日：2012-07-03

申请号：US11753926

申请日：2007-05-25

Applicant: Valli Arunachalam ,  Satyavolu Srinivas Papa Rao ,  Sanjeev Aggarwal ,  Stephan Grunow

Inventor： Valli Arunachalam ,  Satyavolu Srinivas Papa Rao ,  Sanjeev Aggarwal ,  Stephan Grunow

IPC: H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer.

Abstract translation: 根据本发明，存在扩散阻挡层，集成电路和半导体器件及其制造方法。 制造扩散阻挡层的方法可以包括提供电介质层，通过将电介质层暴露于含硅环境，在介电层上形成第一富硅层，并在第一富硅层上形成阻挡层。

公开(公告)号：US07674707B2

公开(公告)日：2010-03-09

申请号：US11968093

申请日：2007-12-31

Applicant: Noel M. Russell ,  Satyavolu Srinivas Papa Rao ,  Stephan Grunow

Inventor： Noel M. Russell ,  Satyavolu Srinivas Papa Rao ,  Stephan Grunow

IPC: H01L21/283

CPC classification number: C23C14/0641 ,  C23C14/0073 ,  H01L21/2855 ,  H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal layer are formed using a physical vapor deposition (PVD) process that requires multiple ignition steps, and results in nitride-layer thicknesses of no less than 2 nm. This invention discloses devices and process to produce nitride-layers of less than

Abstract translation: 提供了设备和方法来在衬底上制造扩散阻挡层。 目前，使用需要多个点火步骤的物理气相沉积（PVD）工艺形成包括氮化物层和纯金属层的阻挡层，并且导致不小于2nm的氮化物层厚度。 本发明公开了生产小于1nm的氮化物层的装置和方法，同时允许在氮化物层上形成纯金属层而不再等离子体。 为了达到这个目的，在等离子体被点燃之前或在形成连续流动等离子体之前，氮气流被切断。 这确保了有限数量的氮原子与基底上的金属原子结合沉积，从而允许氮化物层的受控厚度。

公开(公告)号：US07642619B2

公开(公告)日：2010-01-05

申请号：US12489773

申请日：2009-06-23

Applicant: Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

Inventor： Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

IPC: H01L29/00

CPC classification number: H01L28/10 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction via is formed through the intra-metal dielectric layer and inter-level dielectric layer. An air gap is formed between inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process, and forming a non-conformal layer to seal the extraction via. The air gap may be filled with an inert gas, like argon or nitrogen.

Abstract translation: 诸如电感器的半导体器件形成有气隙。 第一级具有包括一个或多个电感器环，一个或多个通孔和一个或多个铜隔板结构的金属间介电层。 在第一级上形成层间电介质层。 通过金属介电层和层间电介质层形成提取孔。 通过使用超临界流体过程去除与金属介电层相连的金属介电层中的部分，形成不均匀层以密封提取孔，从而在电感器环之间形成气隙。 空气间隙可以填充惰性气体，如氩气或氮气。

公开(公告)号：US20090087956A1

公开(公告)日：2009-04-02

申请号：US11862668

申请日：2007-09-27

Applicant: Satyavolu Srinivas Papa Rao ,  Mona M. Eissa ,  Christopher Lyle Borst ,  Noel M. Russell ,  Stanley Monroe Smith

Inventor： Satyavolu Srinivas Papa Rao ,  Mona M. Eissa ,  Christopher Lyle Borst ,  Noel M. Russell ,  Stanley Monroe Smith

IPC: H01L21/8238 ,  H01L21/4763

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: State of the art Integrated Circuits (ICs) encompass a variety of circuits, which have a wide variety of contact densities as measured in regions from 10 to 1000 microns in size. Fabrication processes for contacts have difficulty with high and low contact densities on the same IC, leading to a high incidence of electrical shorts and reduced operating speed of the circuits. This problem is expected to worsen as feature sizes shrink in future technology nodes. This invention is an electrically non-functional contact, known as a dummy contact, that is utilized to attain a more uniform distribution of contacts across an IC, which allows contact fabrication processes to produce ICs with fewer defects, and a method for forming said dummy contacts in ICs.

Abstract translation: 最先进的集成电路（IC）包括各种电路，其具有在10至1000微米尺寸的区域中测量的各种接触密度。 触点的制造过程在同一个IC上具有高和低接触密度的困难，导致电短路的高发生率和电路的降低的操作速度。 随着未来技术节点的特征尺寸缩小，这个问题预计会恶化。 本发明是被称为虚拟接触件的电非功能性接触件，其用于实现跨越IC的更均匀的接触分布，这允许接触制造工艺制造具有较少缺陷的IC，以及用于形成所述虚拟器件的方法 IC中的联系人

公开(公告)号：US20090001510A1

公开(公告)日：2009-01-01

申请号：US11771298

申请日：2007-06-29

Applicant: Phillip D Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

Inventor： Phillip D Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

IPC: H01L29/00 ,  H01L21/02

CPC classification number: H01L28/10 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.

Abstract translation: 根据本发明，具有气隙的电感器，半导体器件，集成电路及其制造方法。 制造具有气隙的电感器的方法可以包括在包括一个或多个电感器环路，一个或多个通孔以及一个或多个铜隔板结构的金属间介电层中制造第一级电感器，形成级间 电介质层，并且重复步骤以形成两个或更多级别的电感器。 该方法还可以包括形成提取通孔，通过使用超临界流体过程去除与金属介电层相连的部分金属介电层，从而在电感器环之间形成气隙，并形成非共形层以密封提取 通过。