公开(公告)号：US20120238092A1

公开(公告)日：2012-09-20

申请号：US13482550

申请日：2012-05-29

Applicant: Noel Russell ,  John J. Hautala ,  John Gumpher

Inventor： Noel Russell ,  John J. Hautala ,  John Gumpher

IPC: H01L21/283

CPC classification number: H01L21/28506 ,  C23C14/02 ,  C23C14/024 ,  C23C14/16 ,  C23C14/5833 ,  H01J37/08 ,  H01J37/317 ,  H01J2237/0812 ,  H01J2237/3165 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/3205

Abstract: A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region.

Abstract translation: 对半导体装置的制造方法进行说明。 该方法包括在形成硅化物区域期间对含硅衬底的至少一部分进行气体簇离子束（GCIB）的预处理和/或后处理。

公开(公告)号：US20110084216A1

公开(公告)日：2011-04-14

申请号：US12575887

申请日：2009-10-08

Applicant: John J. Hautala ,  Noel Russell

Inventor： John J. Hautala ,  Noel Russell

IPC: G21K5/04 ,  G21K5/10 ,  H01J3/14

CPC classification number: H01J37/3178 ,  C23C14/221 ,  C23C14/50 ,  H01J37/3053 ,  H01J2237/31701 ,  H01J2237/3171 ,  H01J2237/31732 ,  H01J2237/3174 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/26586 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A method for treating a structure is described. One embodiment includes forming a structure on a substrate, wherein the structure has a plurality of surfaces including one or more first surfaces lying substantially parallel to a first plane parallel with said substrate and one or more second surfaces lying substantially perpendicular to the first plane. Additionally, the method comprises directing a gas cluster ion beam (GCIB) formed from a material source toward the substrate with a direction of incidence, and orienting the substrate relative to the direction of incidence. The method further comprises treating the one or more second surfaces.

Abstract translation: 描述了一种处理结构的方法。 一个实施例包括在基底上形成结构，其中该结构具有包括一个或多个第一表面的多个表面，该第一表面基本上平行于与所述基底平行的第一平面，以及基本上垂直于第一平面的一个或多个第二表面。 此外，该方法包括将由材料源形成的气体簇离子束（GCIB）引导到具有入射方向的衬底，并且使衬底相对于入射方向取向。 该方法还包括处理一个或多个第二表面。

公开(公告)号：US07435672B2

公开(公告)日：2008-10-14

申请号：US10903716

申请日：2004-07-30

Applicant: Doufeng Yue ,  Noel Russell ,  Peijun J. Chen ,  Douglas E. Mercer

Inventor： Doufeng Yue ,  Noel Russell ,  Peijun J. Chen ,  Douglas E. Mercer

IPC: H01L21/3205

CPC classification number: H01L21/28518 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by physical vapor deposition, germanium atoms (120) and transition metal atoms (130) to form a metal-germanium alloy layer (140) on a semiconductor substrate (150). The metal-germanium alloy layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (400).

Abstract translation: 本发明提供一种制造用于半导体器件（110）的金属硅化物电极（100）的方法。 该方法包括通过物理气相沉积，锗原子（120）和过渡金属原子（130）沉积以在半导体衬底（150）上形成金属 - 锗合金层（140）。 使金属锗合金层和半导体基板反应形成金属硅化物电极。 本发明的其它方面包括制造集成电路（400）的方法。

公开(公告)号：US20060121724A1

公开(公告)日：2006-06-08

申请号：US11002935

申请日：2004-12-02

Applicant: Duofeng Yue ,  Stephan Grunow ,  Satyavolu Papa Rao ,  Noel Russell ,  Montray Leavy

Inventor： Duofeng Yue ,  Stephan Grunow ,  Satyavolu Papa Rao ,  Noel Russell ,  Montray Leavy

IPC: H01L21/4763

CPC classification number: H01L21/76814 ,  H01L21/2855 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865

Abstract: The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.

Abstract translation: 本发明提供了一种在半导体衬底100上形成互连的方法。 该方法包括在开口130的内表面上形成开口230，沉积物在开口130的顶部附近形成折入轮廓。 势垒230的一部分被蚀刻，其移除阻挡物230的至少一部分以减少折返轮廓。 蚀刻还去除了开口130底部的阻挡物230层的至少一部分。

公开(公告)号：US20060024938A1

公开(公告)日：2006-02-02

申请号：US10901697

申请日：2004-07-29

Applicant: Duofeng Yue ,  Peijun Chen ,  Jiong-Ping Lu ,  Thomas Bonifield ,  Noel Russell

Inventor： Duofeng Yue ,  Peijun Chen ,  Jiong-Ping Lu ,  Thomas Bonifield ,  Noel Russell

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/6656 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653

Abstract: The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor device, and a semiconductor device. The method for manufacturing a semiconductor device, among other steps, includes forming source/drain regions (290) in a substrate (210), the source/drain regions (290) located proximate a gate structure having sidewall spacers (270) and positioned over the substrate (210), and modifying a footprint of the sidewall spacers (270) by forming protective regions (410) proximate a base of the sidewall spacers (270). The method further includes forming metal silicide regions (610) in the source/drain regions (290).

Abstract translation: 本发明提供一种半导体器件的制造方法以及包括该半导体器件的集成电路的制造方法以及半导体器件。 除了其他步骤之外，制造半导体器件的方法包括在衬底（210）中形成源极/漏极区域（290），源/漏极区域（290）位于具有侧壁间隔物（270）的栅极结构附近并定位在 衬底（210），并且通过在侧壁间隔物（270）的基部附近形成保护区（410）来修改侧壁间隔物（270）的覆盖区。 该方法还包括在源/漏区（290）中形成金属硅化物区（610）。

公开(公告)号：US06693357B1

公开(公告)日：2004-02-17

申请号：US10388042

申请日：2003-03-13

Applicant: Christopher Lyle Borst ,  Alwin J. Tsao ,  Bobby David Strong ,  Noel Russell

Inventor： Christopher Lyle Borst ,  Alwin J. Tsao ,  Bobby David Strong ,  Noel Russell

IPC: H01L2348

CPC classification number: H01L21/3212 ,  H01L21/31053 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during metalization processing. One approach employs fill structures of varying sizes where smaller fill structures are formed near wiring regions having high aspect ratio wiring structures and larger fill structures are located near wiring regions with lower aspect ratio wiring structures. Another approach provides fill structures with varying amounts of openings, with fill structures having few or no openings being provided near low aspect ratio wiring structures and fill structures having more openings being located near higher aspect ratio wiring structures.

Abstract translation: 公开了半导体器件及其制造方法，其中在导电布线结构之间的互连布线层中的填充区域中提供导电填充结构，以促进金属化处理期间的平坦化均匀性。 一种方法采用不同尺寸的填充结构，其中在具有高纵横比布线结构的布线区域附近形成较小的填充结构，并且较大的填充结构位于具有较低纵横比布线结构的布线区附近。 另一种方法提供具有不同数量的开口的填充结构，其中填充结构在低纵横比布线结构附近提供很少的或没有开口，并且具有更多开口的填充结构位于较高纵横比布线结构附近。

公开(公告)号：US08226835B2

公开(公告)日：2012-07-24

申请号：US12399449

申请日：2009-03-06

Applicant: John J. Hautala ,  Edmund Burke ,  Noel Russell ,  Gregory Herdt

Inventor： John J. Hautala ,  Edmund Burke ,  Noel Russell ,  Gregory Herdt

IPC: H01L21/44

CPC classification number: C23C14/221 ,  H01L21/02112 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/31144 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/7684 ,  Y10S438/902

Abstract: A method of preparing a thin film on a substrate is described. The method comprises forming an ultra-thin hermetic film over a portion of a substrate using a gas cluster ion beam (GCIB), wherein the ultra-thin hermetic film has a thickness less than approximately 5 nm. The method further comprises providing a substrate in a reduced-pressure environment, and generating a GCIB in the reduced-pressure environment from a pressurized gas mixture. A beam acceleration potential and a beam dose are selected to achieve a thickness of the thin film less than about 5 nanometers (nm). The GCIB is accelerated according to the beam acceleration potential, and the accelerated GCIB is irradiated onto at least a portion of the substrate according to the beam dose. By doing so, the thin film is formed on the at least a portion of the substrate to achieve the thickness desired.

Abstract translation: 描述了在衬底上制备薄膜的方法。 该方法包括使用气体簇离子束（GCIB）在衬底的一部分上形成超薄密封膜，其中超薄密封膜的厚度小于约5nm。 该方法还包括在减压环境中提供衬底，以及在减压环境中从加压气体混合物产生GCIB。 选择光束加速电位和光束剂量以实现小于约5纳米（nm）的薄膜的厚度。 GCIB根据光束加速电位被加速，并且根据光束剂量将加速的GCIB照射到基底的至少一部分上。 通过这样做，薄膜形成在基板的至少一部分上以获得期望的厚度。

公开(公告)号：US08192805B2

公开(公告)日：2012-06-05

申请号：US12338582

申请日：2008-12-18

Applicant: Noel Russell ,  Steven Sherman ,  John J. Hautala

Inventor： Noel Russell ,  Steven Sherman ,  John J. Hautala

IPC: C23C14/48 ,  C23C14/02 ,  C23C14/58 ,  B05D5/12 ,  B05D3/06 ,  H01L21/3115 ,  H01L21/3215

CPC classification number: H01L21/76829 ,  H01L21/3115 ,  H01L21/3221 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76883 ,  H01L29/518

Abstract: Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 这里通常描述了用于改善半导体器件中的漏电性能和最小化电迁移的方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US07981483B2

公开(公告)日：2011-07-19

申请号：US11863036

申请日：2007-09-27

Applicant: Noel Russell ,  Steven Sherman ,  John J. Hautala

Inventor： Noel Russell ,  Steven Sherman ,  John J. Hautala

IPC: C23C14/06 ,  C23C14/08 ,  C23C14/48 ,  H01L21/302 ,  H01L21/3115 ,  H01L21/3215

CPC classification number: H01L21/76849 ,  H01J2237/0812 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76867

Abstract: Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 这里通常描述了用于改善半导体器件中的漏电性能和最小化电迁移的方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US07871929B2

公开(公告)日：2011-01-18

申请号：US12369376

申请日：2009-02-11

Applicant: Noel Russell ,  Frank M. Cerio, Jr. ,  Gregory Herdt

Inventor： Noel Russell ,  Frank M. Cerio, Jr. ,  Gregory Herdt

IPC: H01L21/44

CPC classification number: H01L23/53238 ,  C23C14/04 ,  C23C14/14 ,  C23C14/5833 ,  C23C14/5846 ,  C23C16/04 ,  C23C16/06 ,  C23C16/56 ,  H01J2237/0812 ,  H01L21/02074 ,  H01L21/76825 ,  H01L21/76849 ,  H01L21/76859 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices containing metal cap layers. According to one embodiment, a method of forming a semiconductor device includes planarizing a top surface of a workpiece to form a substantially planar surface with conductive paths and dielectric regions, forming metal cap layers on the conductive paths, and exposing the top surface of the workpiece to a dopant source from a gas cluster ion beam (GCIB) to form doped metal cap layers on the conductive paths and doped dielectric layers on the dielectric regions. According to some embodiments, the metal cap layers and the doped metal cap layers contain a noble metal selected from Pt, Au, Ru, Rh, Ir, and Pd.

Abstract translation: 用于提高漏电性能并使包含金属盖层的半导体器件中的电迁移最小化的方法。 根据一个实施例，一种形成半导体器件的方法包括平坦化工件的顶表面以形成具有导电路径和电介质区域的基本平坦的表面，在导电路径上形成金属帽层，并暴露工件的顶表面 到来自气体簇离子束（GCIB）的掺杂剂源，以在电介质区域上的导电路径上和掺杂的电介质层上形成掺杂金属盖层。 根据一些实施例，金属盖层和掺杂金属盖层含有选自Pt，Au，Ru，Rh，Ir和Pd的贵金属。