公开(公告)号：US06818936B2

公开(公告)日：2004-11-16

申请号：US10288197

申请日：2002-11-05

Applicant: Chrong Jun Lin ,  Hsin-Ming Chen

Inventor： Chrong Jun Lin ,  Hsin-Ming Chen

IPC: H01L27108

CPC classification number: H01L28/40 ,  H01L21/28273 ,  H01L28/91 ,  H01L29/42324 ,  H01L29/66825

Abstract: A single-poly EEPROM cell is disclosed with a vertically formed metal-insulator-metal (MIM) coupling capacitor, which serves as a control gate in place of a laterally buried control gate thereby eliminating the problem of junction breakdown, and at the same time reducing the size of the cell substantially. A method of forming the single-poly cell is also disclosed. This is accomplished by forming a floating gate over a substrate with an intervening tunnel oxide and then the MIM capacitor over the floating gate with another intervening dielectric layer between the top metal and the lower metal of the capacitor where the latter metal is connected to the polysilicon floating gate.

Abstract translation: 公开了具有垂直形成的金属 - 绝缘体 - 金属（MIM）耦合电容器的单聚电解质电池单元，其用作控制栅极以代替横向埋设的控制栅极，从而消除了结击穿的问题，并且同时 基本上减小了细胞的大小。 还公开了形成单多晶硅电池的方法。 这是通过在衬底上形成具有中间隧道氧化物的浮动栅极，然后在浮动栅极上形成MIM电容器，在电容器的顶部金属和下部金属之间的另一个中间介电层，其中后者金属连接到多晶硅 浮动门。

公开(公告)号：US06803625B2

公开(公告)日：2004-10-12

申请号：US10627013

申请日：2003-07-25

Applicant: Chia-Ta Hsieh ,  Di Son Kuo ,  Chrong-Jun Lin ,  Wen-Ting Chu

Inventor： Chia-Ta Hsieh ,  Di Son Kuo ,  Chrong-Jun Lin ,  Wen-Ting Chu

IPC: H01L2978

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is formed in the source region and the walls are sloped to have a tilt. A source implant is performed at a tilt angle and the trench is lined with a gate oxide layer. Subsequently, a lateral diffusion of the source implant is performed followed by thermal cycling. The lateral enlargement of the diffused source is found to increase the coupling ratio of the split-gate flash memory cell substantially.

公开(公告)号：US06624025B2

公开(公告)日：2003-09-23

申请号：US09940158

申请日：2001-08-27

Applicant: Chia-Ta Hsieh ,  Di Son Kuo ,  Chrong-Jun Lin ,  Wen-Ting Chu

Inventor： Chia-Ta Hsieh ,  Di Son Kuo ,  Chrong-Jun Lin ,  Wen-Ting Chu

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is formed in the source region and the walls are sloped to have a tilt. A source implant is performed at a tilt angle and the trench is lined with a gate oxide layer. Subsequently, a lateral diffusion of the source implant is performed followed by thermal cycling. The lateral enlargement of the diffused source is found to increase the coupling ratio of the split-gate flash memory cell substantially.

Abstract translation: 提供了具有倾斜沟槽源的改进的编程和擦除速度的分裂栅极闪存单元，以及其形成方法。 这通过形成两个浮动栅极和它们各自的控制栅极共享公共源极区域来实现。 在源区域中形成沟槽，并且壁倾斜以具有倾斜。 以倾斜角进行源植入，并且沟槽衬有栅极氧化物层。 随后，进行源植入物的横向扩散，然后进行热循环。 发现扩散源的横向放大基本上增加了分裂栅极闪存单元的耦合比。