公开(公告)号：US20160172361A1

公开(公告)日：2016-06-16

申请号：US15049792

申请日：2016-02-22

申请人： Hwa-Sung Rhee ,  Seung-Chul LEE ,  Chul-Wan AN ,  Henry K. UTOMO ,  Seong-Dong KIM

发明人： Hwa-Sung Rhee ,  Seung-Chul LEE ,  Chul-Wan AN ,  Henry K. UTOMO ,  Seong-Dong KIM

IPC分类号： H01L27/092 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

摘要： Methods of forming field effect transistors include selectively etching source and drain region trenches into a semiconductor region using a gate electrode as an etching mask. An epitaxial growth process is performed to fill the source and drain region trenches. Silicon germanium (SiGe) source and drain regions may be formed using an epitaxial growth process. During this growth process the bottoms and sidewalls of the trenches may be used as “seeds” for the silicon germanium growth. An epitaxial growth step may then be performed to define silicon capping layers on the SiGe source and drain regions.

摘要翻译： 形成场效应晶体管的方法包括使用栅电极作为蚀刻掩模来选择性地将源极和漏极区沟槽刻蚀成半导体区域。 执行外延生长工艺以填充源极和漏极区沟槽。 可以使用外延生长工艺来形成硅锗（SiGe）源极和漏极区。 在该生长过程中，沟槽的底部和侧壁可以用作硅锗生长的“种子”。 然后可以执行外延生长步骤以在SiGe源极和漏极区上限定硅覆盖层。

公开(公告)号：US20130149830A1

公开(公告)日：2013-06-13

申请号：US13313881

申请日：2011-12-07

申请人： Hwa-Sung RHEE ,  Seung-Chul Lee ,  Chul-Wan An ,  Henry K. Utomo ,  Seong-Dong Kim

发明人： Hwa-Sung RHEE ,  Seung-Chul Lee ,  Chul-Wan An ,  Henry K. Utomo ,  Seong-Dong Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

摘要： Methods of forming field effect transistors include selectively etching source and drain region trenches into a semiconductor region using a gate electrode as an etching mask. An epitaxial growth process is performed to fill the source and drain region trenches. Silicon germanium (SiGe) source and drain regions may be formed using an epitaxial growth process. During this growth process, the bottoms and sidewalls of the trenches may be used as “seeds” for the silicon germanium growth. An epitaxial growth step may then be performed to define silicon capping layers on the SiGe source and drain regions.

摘要翻译： 形成场效应晶体管的方法包括使用栅电极作为蚀刻掩模来选择性地将源极和漏极区沟槽刻蚀成半导体区域。 执行外延生长工艺以填充源极和漏极区沟槽。 可以使用外延生长工艺来形成硅锗（SiGe）源极和漏极区。 在该生长过程中，沟槽的底部和侧壁可以用作硅锗生长的“种子”。 然后可以执行外延生长步骤以在SiGe源极和漏极区上限定硅覆盖层。

公开(公告)号：US20060046456A1

公开(公告)日：2006-03-02

申请号：US11204469

申请日：2005-08-15

申请人： Chul-wan An

发明人： Chul-wan An

IPC分类号： H01L21/44

CPC分类号： H01L21/76807 ,  H01L21/2885 ,  H01L21/76847 ,  H01L21/76879 ,  H01L23/485

摘要： The present invention is directed to a damascene process using different kinds of metals is provided. An interlayer dielectric is formed to cover a semiconductor substrate. A contact hole is formed to expose the semiconductor substrate through the interlayer dielectric. A groove is formed to overlap the contact hole. A first barrier metal layer is conformally formed. A first seed layer is conformally formed. A first conductive layer is formed to fill a contact hole below the groove. A second conductive layer is formed to fill the groove. According to the damascene process, a CMP process for a tungsten layer is not needed such that total process cost is reduced and the overall general process is simplified.

摘要翻译： 本发明涉及一种使用不同种类金属的镶嵌工艺。 形成层间电介质以覆盖半导体衬底。 形成接触孔以通过层间电介质暴露半导体衬底。 形成有与接触孔重叠的槽。 第一阻挡金属层保形地形成。 第一种子层是共形形成的。 形成第一导电层以填充凹槽下方的接触孔。 形成第二导电层以填充凹槽。 根据镶嵌工艺，不需要用于钨层的CMP工艺，从而减少总工艺成本并简化总的整体工艺。