公开(公告)号：US20240363409A1

公开(公告)日：2024-10-31

申请号：US18771313

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chen-Yuan Kao ,  Yi-Wei Chiu ,  Liang-Yueh Ou Yang ,  Yueh-Ching Pai

IPC分类号： H01L21/768 ,  H01L21/285 ,  H01L21/288 ,  H01L23/485 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/76895 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L29/41775 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/7833 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L23/485

摘要： A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

公开(公告)号：US20240162811A1

公开(公告)日：2024-05-16

申请号：US18485913

申请日：2023-10-12

申请人： Redwood Materials, Inc.

发明人： Patrick Chapman ,  Jaesoo Byoun ,  David Okawa ,  Anton Hunt ,  Isaac Thomas ,  Guillermo Urquiza ,  Roger Bishop

IPC分类号： H02M3/00 ,  H01L21/288 ,  H05K7/14

CPC分类号： H02M3/003 ,  H01L21/2885 ,  H05K7/14322

摘要： The present disclosure relates to systems, non-transitory computer-readable media, and methods for applying controllable current to portions of an electrodeposition device via a series-in-parallel-out rectifier circuit. In particular, the rectifier circuit includes a front-end stage that includes an alternating current-to-direct current converter circuit to generate one or more direct current signals from an alternating current signal of an input terminal. Additionally, the rectifier circuit includes a back-end stage including a plurality of direct current-to-direct current converter circuits that convert the one or more direct current signals into a plurality of child direct current signals. Furthermore, the plurality of direct current-to-direct current converter circuits of the disclosed series-in-parallel-out rectifier circuit are in physical contact with an anode of the electrodeposition device at a plurality of different positions to apply separate currents to different portions of the anode.

公开(公告)号：US20240145251A1

公开(公告)日：2024-05-02

申请号：US17974426

申请日：2022-10-26

申请人： Applied Materials, Inc.

发明人： Kyle M. Hanson

IPC分类号： H01L21/288 ,  C25D17/00 ,  C25D17/10 ,  H01L21/67 ,  H01L21/687 ,  H01L21/768

CPC分类号： H01L21/2885 ,  C25D17/007 ,  C25D17/10 ,  H01L21/6723 ,  H01L21/68764 ,  H01L21/76873

摘要： Conditions at the perimeter of the wafer may be characterized and used to adjust current stolen by the weir thief electrodes during a plating process to generate more uniform film thicknesses. An electrode may be positioned in a plating chamber near the periphery of the wafer as the wafer rotates. To characterize the electrical contacts on the seal, a wafer with a seed layer may be loaded into the plating chamber, and a constant current may be driven through the electrode into the conductive layer on the wafer. As an electrical characteristic of this current varies, such as a voltage required to drive a constant current, a mapping characterizing the seal quality or the openings in the mask layer may be generated.

公开(公告)号：US11973034B2

公开(公告)日：2024-04-30

申请号：US17411321

申请日：2021-08-25

申请人： Applied Materials, Inc.

发明人： Eric J. Bergman ,  John L. Klocke ,  Marvin L. Bernt ,  Jing Xu ,  Kwan Wook Roh

IPC分类号： H01L23/532 ,  C25D3/38 ,  C25D5/48 ,  C25D7/12 ,  H01L21/288 ,  H01L21/768

CPC分类号： H01L23/53238 ,  C25D3/38 ,  C25D5/48 ,  C25D7/12 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/53252

摘要： Exemplary methods of electroplating a metal with a nanotwin crystal structure are described. The methods may include plating a metal material into at least one opening on a patterned substrate, where at least a portion of the metal material is characterized by a nanotwin crystal structure. The methods may further include polishing an exposed surface of the metal material in the opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm. The polished exposed surface may include at least a portion of the metal material characterized by the nanotwin crystal structure. In additional examples, the nanotwin-phased metal may be nanotwin-phased copper.

公开(公告)号：US11920254B2

公开(公告)日：2024-03-05

申请号：US17460500

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yung Chang Huang

IPC分类号： C25D21/12 ,  C25D7/12 ,  C25D17/00 ,  C25D17/06 ,  H01L21/288

CPC分类号： C25D21/12 ,  C25D7/123 ,  C25D17/001 ,  C25D17/06 ,  H01L21/2885

摘要： The present disclosure relates to an electroplating system including a first contact detection sensor and a second contact detection sensor disposed at a surface of a cone of the electroplating system. The first contact detection sensor detects a first resistance at a first contact between a substrate to be plated by the electroplating system and a first contact pin, the second contact detection sensor detects a second resistance at a second contact between the substrate and a second contact pin. A controller receives the first resistance and the second resistance, and determines the first contact and the second contact are not properly formed when a difference between the first resistance and the second resistance is not within a first predetermined resistance range, or the first resistance or the second resistance is not within a second predetermined resistance range.

公开(公告)号：US20240018678A1

公开(公告)日：2024-01-18

申请号：US18372236

申请日：2023-09-25

申请人： MacDermid Enthone Inc.

发明人： Vincent Paneccasio, JR. ,  Kyle Whitten ,  Richard Hurtubise ,  John Commander ,  Eric Rouya

IPC分类号： C25D3/38 ,  C25D7/12 ,  C25D17/00

CPC分类号： C25D3/38 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885

摘要： An electrolytic plating composition for superfilling submicron features in a semiconductor integrated circuit device and a method of using the same. The composition comprises (a) a source of copper ions to electrolytically deposit copper onto the substrate and into the electrical interconnect features, and (b) a suppressor comprising at least three amine sites, said polyether comprising a block copolymer substituent comprising propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units, wherein the number average molecular weight of the suppressor compound is between about 1,000 and about 20,000.

公开(公告)号：US11859300B2

公开(公告)日：2024-01-02

申请号：US17809124

申请日：2022-06-27

申请人： Lam Research Corporation

发明人： Zhian He ,  Shantinath Ghongadi ,  Quan Ma ,  Hyungjun Hur ,  Cian Sweeney ,  Quang Nguyen ,  Rezaul Karim ,  Jingbin Feng

IPC分类号： C25D17/00 ,  C25D17/10 ,  C25D3/38 ,  C25D21/14 ,  C25D21/18 ,  H01L21/288

CPC分类号： C25D17/001 ,  C25D3/38 ,  C25D17/002 ,  C25D17/10 ,  C25D21/14 ,  C25D21/18 ,  H01L21/2885

摘要： Methods and electroplating systems for controlling plating electrolyte concentration on an electrochemical plating apparatus for substrates are disclosed. A method involves: (a) providing an electroplating solution to an electroplating system; (b) electroplating the metal onto the substrate while the substrate is held in a cathode chamber of an electroplating cell of electroplating system; (c) supplying the make-up solution to the electroplating system via a make-up solution inlet; and (d) supplying the secondary electroplating solution to the electroplating system via a secondary electroplating solution inlet. The secondary electroplating solution includes some or all components of the electroplating solution. At least one component of the secondary electroplating solution has a concentration that significantly deviates from its target concentration.

公开(公告)号：US11854962B2

公开(公告)日：2023-12-26

申请号：US17106766

申请日：2020-11-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Che-Cheng Chang ,  Chih-Han Lin

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/288 ,  H01L23/532 ,  H01L21/027 ,  H01L21/321 ,  H01L29/06

CPC分类号： H01L23/5226 ,  H01L21/0276 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/088 ,  H01L21/3212 ,  H01L21/7684 ,  H01L29/0649

摘要： A semiconductor device includes a substrate, a bottom etch stop layer over the substrate, a middle etch stop layer over the bottom etch stop layer, and a top etch stop layer over the middle etch stop layer. The top, middle, and bottom etch stop layers include different material compositions from each other. The semiconductor device further includes a dielectric layer over the top etch stop layer and a via extending through the dielectric layer and the top, middle, and bottom etch stop layers. The via has a first sidewall in contact with the dielectric layer and slanted inwardly from top to bottom towards a center of the via and a second sidewall in contact with the bottom etch stop layer and slanted outwardly from top to bottom away from the center of the via.

公开(公告)号：US11837595B2

公开(公告)日：2023-12-05

申请号：US16727925

申请日：2019-12-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Cheng-Ying Ho ,  Wen-De Wang ,  Jen-Cheng Liu ,  Dun-Nian Yaung

IPC分类号： H01L21/762 ,  H01L25/00 ,  H01L23/522 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/285 ,  H01L21/288 ,  H01L23/532

CPC分类号： H01L25/50 ,  H01L21/2855 ,  H01L21/2885 ,  H01L21/76251 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L21/76805 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/245 ,  H01L2224/24145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/82106 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2224/82106 ,  H05K3/467 ,  H01L2224/245 ,  H01L2924/01029 ,  H01L2224/245 ,  H01L2924/01079 ,  H01L2224/245 ,  H01L2924/01047 ,  H01L2224/245 ,  H01L2924/01028 ,  H01L2224/245 ,  H01L2924/01074 ,  H01L2224/245 ,  H01L2924/01013 ,  H01L2224/245 ,  H01L2924/01046 ,  H01L2224/9212 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/9212 ,  H01L2224/80001 ,  H01L2224/82

摘要： A semiconductor device structure includes a first chip, second chip, a first metal structure, a second metal structure, a first via structure and a second via structure. The first chip includes n inter metal dielectric (IMD) layer, which includes different materials adjacent to generate a number of staggered portions having a zigzag configuration. The second chip bonded to the first chip generates a bonding interface. The first metal structure is disposed in the first chip and between the staggered portions and the bonding interface. The first via structure in the first chip stops at the first metal structure. The first via structure includes a first via metal and a first via dielectric layer. A surface roughness of the staggered portions is substantially greater than a surface roughness of the first via dielectric layer. The second via structure extends from the first via structure to the second metal structure.

公开(公告)号：US20230386824A1

公开(公告)日：2023-11-30

申请号：US18231196

申请日：2023-08-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kuo-Lung HOU ,  Ming-Hsien LIN

IPC分类号： H01L21/02 ,  C25D21/12 ,  C25D7/12 ,  C25D5/54 ,  H01L21/67 ,  B08B13/00 ,  H01L21/288 ,  H01L21/66 ,  B08B3/08 ,  B08B3/02

CPC分类号： H01L21/02087 ,  C25D21/12 ,  C25D7/12 ,  C25D5/54 ,  H01L21/67051 ,  B08B13/00 ,  H01L21/2885 ,  H01L22/26 ,  B08B3/08 ,  B08B3/02 ,  H01L21/67253

摘要： An electrochemical plating apparatus for performing an edge bevel removal process on a wafer includes a cell chamber. The cell chamber includes two or more nozzles located adjacent to the edge of the wafer. A flow regulator is arranged with each of the two or more nozzles, which is configured to regulate a tap width of a deposited film flowing out through the each of the two or more nozzles. The electrochemical plating apparatus further includes a controller to control the flow regulator such that tap width of the deposited film includes a pre-determined surface profile. The two or more nozzles are located in radially or angularly different dispensing positions above the wafer.