公开(公告)号：US20130005191A1

公开(公告)日：2013-01-03

申请号：US13401775

申请日：2012-02-21

申请人： Jun ZHANG ,  Chun-Sheng LI ,  Jian-Jun MA ,  Bin PENG ,  Jun WANG ,  Le-Juan YU ,  Yan TIAN

发明人： Jun ZHANG ,  Chun-Sheng LI ,  Jian-Jun MA ,  Bin PENG ,  Jun WANG ,  Le-Juan YU ,  Yan TIAN

IPC分类号： H01R24/76

CPC分类号： H01R13/422 ,  H01R12/722 ,  H01R24/28

摘要： An electrical connector includes an insulative housing, a first contact and a central contact being of a uni-configuration respectively retained in the housing. The housing has a mating cavity extending through a front face thereof, a receiving hole extending through a rear face thereof, and a projection rearwards projecting from the rear face. The projection defines a retaining slot opened sideward and a supporting portion disposed between the retaining slot and the rear face of the housing, a connecting portion of the central contact climbs over the supporting portion and runs through the retaining slot.

摘要翻译： 电连接器包括绝缘壳体，第一触点和分别保持在壳体中的单一构造的中心触点。 壳体具有延伸穿过其前表面的配合腔，延伸穿过其背面的接收孔和从后表面向后突出的突起。 突起限定了侧向敞开的保持槽和设置在保持槽和壳体的后表面之间的支撑部分，中心触点的连接部分爬过支撑部分并且穿过保持槽。

公开(公告)号：US08288774B2

公开(公告)日：2012-10-16

申请号：US13348715

申请日：2012-01-12

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/04 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/15 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L31/108

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a shaped of L- or of snake from top-view, having a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the poly-Si layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the poly-Si layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line through a source contact.

摘要翻译： 公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。 该布局包括（1）在基底上的多晶硅，其具有顶部具有L-或蛇形的形状，具有重掺杂的源极区，第一轻掺杂区，第一栅极通道，第二轻掺杂区， 第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在具有扫描线的栅极氧化物层上形成栅极金属层，并且具有L形或I形的延伸部分 。 栅极金属与多晶硅层相交，限定了前述栅极沟道。 在栅极通道中，至少有一个沿着信号线通过源极接触。

公开(公告)号：US20090230403A1

公开(公告)日：2009-09-17

申请号：US12469298

申请日：2009-05-20

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L29/786 ,  H01L33/00

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

公开(公告)号：USD517994S1

公开(公告)日：2006-03-28

申请号：US29224645

申请日：2005-03-03

申请人： An-Yi Zhang ,  Chun-Sheng Li ,  Bing-Cheng Meng

设计人： An-Yi Zhang ,  Chun-Sheng Li ,  Bing-Cheng Meng

公开(公告)号：US20050280030A1

公开(公告)日：2005-12-22

申请号：US11211606

申请日：2005-08-26

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/739

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

摘要翻译： 公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。 布局包括（1）在基板上具有从顶视图形成的L形或蛇形的多晶硅，其具有重掺杂的源极区，第一轻掺杂区，第一栅极沟道，第二轻掺杂区， 第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在栅极氧化物层上形成栅极金属层，栅极氧化物层具有扫描线和具有L形或I形的延伸部分。 栅极金属与多晶硅层相交，限定了前述栅极沟道。 在栅极通道中，沿着信号线至少有一个通过源极接触连接到源极区域。

公开(公告)号：US20110133200A1

公开(公告)日：2011-06-09

申请号：US13026453

申请日：2011-02-14

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L29/04

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

摘要翻译： 公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。 该布局包括：（1）具有从顶部形成的L形或蛇形的衬底上的多晶硅，其具有重掺杂源极区，第一轻掺杂区，第一栅极沟道，第二轻掺杂区域， 第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在栅极氧化物层上形成栅极金属层，栅极氧化物层具有扫描线和具有L形或I形的延伸部分。 栅极金属与多晶硅层相交，限定了前述栅极沟道。 在栅极通道中，沿着信号线至少有一个通过源极接触连接到源极区域。

公开(公告)号：US20100159720A1

公开(公告)日：2010-06-24

申请号：US12512331

申请日：2009-07-30

申请人： Ning Wang ,  Chun-Sheng Li

发明人： Ning Wang ,  Chun-Sheng Li

IPC分类号： H01R12/02 ,  H01R13/631 ,  H01R33/00

CPC分类号： H01R13/6271 ,  H01R12/716 ,  H01R13/447

摘要： An electrical connector adapted for being mounted on a printed circuit board includes a base member loaded with a plurality of contacts therein and defining a mounting face confronting with the printed circuit board on which the base member is mounted, a cover member pivotally supported at a rear end of the base member and rotating between a closed position and an opened position. The cover member covers on the base member in a closed position and rotates to the opened position to define a mating cavity adapted for receiving a counter connector. The mating cavity includes a first mating face defined on the base member and parallel to the mounting face and a second mating face defined on the cover member defined on the cover member and parallel to the mounting face.

摘要翻译： 适于安装在印刷电路板上的电连接器包括：底座，其中装有多个触点，并且限定与安装有基座构件的印刷电路板相对的安装面;在后部枢转地支撑的盖构件 并且在关闭位置和打开位置之间旋转。 盖构件在关闭位置处覆盖在基座构件上并且旋转到打开位置以限定适于接收对接连接器的配合腔。 配合腔包括限定在基底构件上并平行于安装面的第一配合面和限定在盖构件上并平行于安装面的盖构件上的第二配合面。

公开(公告)号：US20090280694A1

公开(公告)日：2009-11-12

申请号：US12384149

申请日：2009-04-01

申请人： Quan Zhuang ,  Chun-Sheng Li ,  Ji-Cheng Wang ,  Li-Zhi Zhang

发明人： Quan Zhuang ,  Chun-Sheng Li ,  Ji-Cheng Wang ,  Li-Zhi Zhang

IPC分类号： H01R24/04

CPC分类号： H01R24/64

摘要： An electrical connector includes an insulating housing having a top wall (13), a bottom wall (19) and side walls (14) to define a receiving cavity (12) opening forward. The top wall (13) defines an opening (15) opened upward and forward. A pair of stopping portions (16) facing to each other being are formed on the top wall (13) and project into the opening (15), each of which includes a lead-in portion at a lower and rear corner thereof. A plurality of contacts (4) are assembled to the insulating housing, each of which includes a contacting portion (41) extending into the receiving cavity (12). A shell (2) is provided to shield the insulating housing (1). The lead-in portion of each stopping portion can provide facility operation during the mating process.

摘要翻译： 电连接器包括具有顶壁（13），底壁（19）和侧壁（14）的绝缘壳体，以限定向前开口的接收腔（12）。 顶壁（13）限定向上和向前敞开的开口（15）。 一对彼此相对的止动部分（16）形成在顶壁（13）上，并突出到开口（15）中，每个在其下角和后角处包括引入部分。 多个触点（4）组装到绝缘壳体上，每个触头包括延伸到接收腔（12）中的接触部分（41）。 提供壳体（2）以屏蔽绝缘壳体（1）。 每个停止部分的引入部分可以在配合过程期间提供设备操作。

公开(公告)号：US20090236606A1

公开(公告)日：2009-09-24

申请号：US12469280

申请日：2009-05-20

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L29/786 ,  H01L33/00

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

摘要翻译： 公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。 布局包括（1）在基板上具有从顶视图形成的L形或蛇形的多晶硅，其具有重掺杂的源极区，第一轻掺杂区，第一栅极沟道，第二轻掺杂区， 第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在具有扫描线的栅极氧化物层和具有L形或I形的延伸部分的栅极金属层上形成栅极金属层。 栅极金属与多晶硅层相交，限定了前述栅极沟道。 在栅极通道中，沿着信号线至少有一个通过源极接触连接到源极区域。

公开(公告)号：US07153147B2

公开(公告)日：2006-12-26

申请号：US11169984

申请日：2005-06-28

申请人： Xue-qing Li ,  Chun-sheng Li ,  Feng Zhu

发明人： Xue-qing Li ,  Chun-sheng Li ,  Feng Zhu

IPC分类号： H01R13/44

CPC分类号： H01R43/205 ,  H01R12/7029 ,  H01R12/716 ,  H01R12/724

摘要： An electrical connector assembly comprising a housing (1) having a mounting face (11) adapted for mounting on a printed circuit board, a top face (12) substantially parallel to the mounting face and a mating face (16) substantially perpendicular to the mounting face, and defining a mating cavity (17) in the mating face thereof; a plurality of terminals (2) received in the housing and each having a contact portion (21 or 22) exposed in the mating cavity; and a releasable pick-up device (200) including a main plate (3) covering the top face of the housing to provide a flat upper surface (30) for receiving suction by a vacuum transfer assembly, and a auxiliary plate (4) perpendicularly extending from the main plate to cover an opening of the mating cavity in the mating face of the housing.