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公开(公告)号：US06833233B2
公开(公告)日：2004-12-21
申请号：US10133613
申请日：2002-04-26
申请人： Chung-Hsiu Cheng , Pin-Yi Hsin , Ming-Chyi Liu , Chih-Hsien Hsu
发明人： Chung-Hsiu Cheng , Pin-Yi Hsin , Ming-Chyi Liu , Chih-Hsien Hsu
IPC分类号： G03F726
CPC分类号： H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A deep ultraviolet (UV) light-resistant photoresist plug for via holes, as may be used in damascene, dual-damascene, and other types of semiconductor fabrication processing, is disclosed. A via hole of a semiconductor wafer is partially plugged with non-photosensitive photoresist, such as negative photoresist. The via hole and the wafer are then coated with a deep UV light-sensitive photoresist. The deep UV light-sensitive photoresist is exposed to deep UV light, such as 193 nanometer (nm) wavelength light, where the non-photosensitive photoresist is unresponsive to the deep UV light. The wafer is then developed to selectively remove the deep UV light-sensitive photoresist, where the non-photosensitive photoresist substantially remains.
摘要翻译： 公开了用于通孔的深紫外（UV）耐光光致抗蚀剂插塞，可用于镶嵌，双镶嵌和其他类型的半导体制造处理。 半导体晶片的通孔部分地被非感光性光致抗蚀剂（例如负性光致抗蚀剂）堵塞。 然后用深UV光敏光刻胶涂覆通孔和晶片。 深紫外光敏光致抗蚀剂暴露于深紫外光，例如193纳米（nm）波长的光，其中非感光性光致抗蚀剂对深紫外光无反应。 然后将晶片显影以选择性地去除深UV光敏光致抗蚀剂，其中非感光性光致抗蚀剂基本保持不变。
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2.发明授权Method of forming a layer on a semiconductor substrate having a plurality of trenches 有权在具有多个沟槽的半导体衬底上形成层的方法公开(公告)号：US08673788B2
公开(公告)日：2014-03-18
申请号：US12845531
申请日：2010-07-28
IPC分类号： H01L21/302 , H01L21/461 , C03C25/00 , C23F1/00 , B44C1/22
CPC分类号： H01L21/32137 , H01L21/31138 , H01L21/32115
摘要： A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.
摘要翻译： 示出了制造半导体器件的方法。 提供具有多个沟槽的衬底。 多个沟槽包括具有不同宽度的沟槽。 在包括在多个沟槽中的衬底上形成第一层。 形成第一层在覆盖沟槽（例如，宽沟槽）的区域中的第一层中形成凹陷。 第二层形成在压痕中。 第一层被蚀刻，而第二层保留在压痕中。 第二层可以保护压痕区域进一步减小厚度。 在一个实施例中，第一层是多晶硅，第二层是光致抗蚀剂的BARC。
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3.发明申请METHOD OF FORMING A LAYER ON A SEMICONDUCTOR SUBSTRATE HAVING A PLURALITY OF TRENCHES 有权在具有多个梯度的半导体基板上形成层的方法公开(公告)号：US20120028468A1
公开(公告)日：2012-02-02
申请号：US12845531
申请日：2010-07-28
IPC分类号： H01L21/02
CPC分类号： H01L21/32137 , H01L21/31138 , H01L21/32115
摘要： A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.
摘要翻译： 示出了制造半导体器件的方法。 提供具有多个沟槽的衬底。 多个沟槽包括具有不同宽度的沟槽。 在包括在多个沟槽中的衬底上形成第一层。 形成第一层在覆盖沟槽（例如，宽沟槽）的区域中的第一层中形成凹陷。 第二层形成在压痕中。 第一层被蚀刻，而第二层保留在压痕中。 第二层可以保护压痕区域进一步减小厚度。 在一个实施例中，第一层是多晶硅，第二层是光致抗蚀剂的BARC。
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