Method of forming a layer on a semiconductor substrate having a plurality of trenches
    1.
    发明授权
    Method of forming a layer on a semiconductor substrate having a plurality of trenches 有权
    在具有多个沟槽的半导体衬底上形成层的方法

    公开(公告)号:US08673788B2

    公开(公告)日:2014-03-18

    申请号:US12845531

    申请日:2010-07-28

    摘要: A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.

    摘要翻译: 示出了制造半导体器件的方法。 提供具有多个沟槽的衬底。 多个沟槽包括具有不同宽度的沟槽。 在包括在多个沟槽中的衬底上形成第一层。 形成第一层在覆盖沟槽(例如,宽沟槽)的区域中的第一层中形成凹陷。 第二层形成在压痕中。 第一层被蚀刻,而第二层保留在压痕中。 第二层可以保护压痕区域进一步减小厚度。 在一个实施例中,第一层是多晶硅,第二层是光致抗蚀剂的BARC。

    METHOD OF FORMING A LAYER ON A SEMICONDUCTOR SUBSTRATE HAVING A PLURALITY OF TRENCHES
    2.
    发明申请
    METHOD OF FORMING A LAYER ON A SEMICONDUCTOR SUBSTRATE HAVING A PLURALITY OF TRENCHES 有权
    在具有多个梯度的半导体基板上形成层的方法

    公开(公告)号:US20120028468A1

    公开(公告)日:2012-02-02

    申请号:US12845531

    申请日:2010-07-28

    IPC分类号: H01L21/02

    摘要: A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.

    摘要翻译: 示出了制造半导体器件的方法。 提供具有多个沟槽的衬底。 多个沟槽包括具有不同宽度的沟槽。 在包括在多个沟槽中的衬底上形成第一层。 形成第一层在覆盖沟槽(例如,宽沟槽)的区域中的第一层中形成凹陷。 第二层形成在压痕中。 第一层被蚀刻,而第二层保留在压痕中。 第二层可以保护压痕区域进一步减小厚度。 在一个实施例中,第一层是多晶硅,第二层是光致抗蚀剂的BARC。

    Projection optical system and light amount adjusting component used in the same
    3.
    发明授权
    Projection optical system and light amount adjusting component used in the same 有权
    投影光学系统和光量调节组件中使用的相同

    公开(公告)号:US07993018B2

    公开(公告)日:2011-08-09

    申请号:US12369343

    申请日:2009-02-11

    IPC分类号: G03B21/20

    摘要: A light amount adjusting component adapted a projection optical system is provided. The light amount adjusting component has a light incident surface upon which a light beam impinges, and the light incident surface is provided with a surface structure for irregularly dispersing the light beam. A slot that permits the light beam to pass therethrough and enter a light-receiving element is formed on the light amount adjusting component, and a width of the slot changes along an extension direction of the slot to allow control of the amount of the light beam entering the light-receiving element when the light amount adjusting component moves or rotates.

    摘要翻译: 提供了适用于投影光学系统的光量调节部件。 光量调节部件具有光入射面,光入射面入射面,光入射面设有用于不规则地分散光束的表面结构。 允许光束通过并进入光接收元件的槽形成在光量调节部件上,并且槽的宽度沿着槽的延伸方向变化,以允许控制光束的量 当光量调节组件移动或旋转时进入光接收元件。

    PROJECTION SCREEN AND MANUFACTURING METHOD OF PROJECTION SCREEN
    4.
    发明申请
    PROJECTION SCREEN AND MANUFACTURING METHOD OF PROJECTION SCREEN 有权
    投影屏幕的投影屏幕和制造方法

    公开(公告)号:US20160004150A1

    公开(公告)日:2016-01-07

    申请号:US14574371

    申请日:2014-12-17

    IPC分类号: G03B21/60 G03B21/58

    CPC分类号: G03B21/60 G03B21/56 G03B21/58

    摘要: A projection screen includes a flexible substrate, a reflective layer and a transparent coating layer. The flexible substrate has a first surface and a second surface opposite to each other. The reflective layer is disposed on the first surface of the flexible substrate. The transparent coating layer is coated on the reflective layer, and the transparent coating layer has a pattern on a surface opposite to the reflective layer. Moreover, a manufacturing method of the projection screen is also provided.

    摘要翻译: 投影屏幕包括柔性基板,反射层和透明涂层。 柔性基板具有彼此相对的第一表面和第二表面。 反射层设置在柔性基板的第一表面上。 透明涂层涂覆在反射层上,透明涂层在与反射层相反的表面上具有图案。 此外,还提供了投影屏幕的制造方法。

    Device housing
    5.
    发明授权
    Device housing 有权
    设备外壳

    公开(公告)号:US08523396B2

    公开(公告)日:2013-09-03

    申请号:US13212203

    申请日:2011-08-18

    申请人: Chia-Chi Chung

    发明人: Chia-Chi Chung

    IPC分类号: F21V33/00

    摘要: A device housing includes first and second cases, a first magnetically sensitive positioning pin, and a first compressible member. The first case has a first protruding block having a first positioning hole. The second case has a first groove having a second positioning hole. When the first protruding block is disposed in the first groove, the first positioning hole is aligned with the second positioning hole. The first magnetically sensitive positioning pin runs through the first and second positioning holes to position the second case on the first case. The first compressible member is disposed in the first positioning hole and between an inner wall of the first positioning hole and the first magnetically sensitive positioning pin. When a first magnetic force acts on the first magnetically sensitive positioning pin, the first magnetically sensitive positioning pin compresses the first compressible member and moves away from the second positioning hole.

    摘要翻译: 装置壳体包括第一和第二壳体,第一磁敏定位销和第一可压缩构件。 第一壳体具有第一突出块,其具有第一定位孔。 第二壳体具有第一凹槽,具有第二定位孔。 当第一突出块设置在第一槽中时,第一定位孔与第二定位孔对准。 第一磁敏定位销穿过第一和第二定位孔,以将第二壳体定位在第一壳体上。 第一可压缩构件设置在第一定位孔中并且位于第一定位孔的内壁和第一磁敏定位销之间。 当第一磁力作用在第一磁敏定位销上时,第一磁敏定位销压缩第一可压缩构件并远离第二定位孔移动。

    DEVICE HOUSING
    6.
    发明申请
    DEVICE HOUSING 有权
    设备外壳

    公开(公告)号:US20120133252A1

    公开(公告)日:2012-05-31

    申请号:US13212203

    申请日:2011-08-18

    申请人: Chia-Chi Chung

    发明人: Chia-Chi Chung

    IPC分类号: G03B21/14

    摘要: A device housing includes first and second cases, a first magnetically sensitive positioning pin, and a first compressible member. The first case has a first protruding block having a first positioning hole. The second case has a first groove having a second positioning hole. When the first protruding block is disposed in the first groove, the first positioning hole is aligned with the second positioning hole. The first magnetically sensitive positioning pin runs through the first and second positioning holes to position the second case on the first case. The first compressible member is disposed in the first positioning hole and between an inner wall of the first positioning hole and the first magnetically sensitive positioning pin. When a first magnetic force acts on the first magnetically sensitive positioning pin, the first magnetically sensitive positioning pin compresses the first compressible member and moves away from the second positioning hole.

    摘要翻译: 装置壳体包括第一和第二壳体,第一磁敏定位销和第一可压缩构件。 第一壳体具有第一突出块,其具有第一定位孔。 第二壳体具有第一凹槽,具有第二定位孔。 当第一突出块设置在第一槽中时,第一定位孔与第二定位孔对准。 第一磁敏定位销穿过第一和第二定位孔,以将第二壳体定位在第一壳体上。 第一可压缩构件设置在第一定位孔中并且位于第一定位孔的内壁和第一磁敏定位销之间。 当第一磁力作用在第一磁敏定位销上时,第一磁敏定位销压缩第一可压缩构件并远离第二定位孔移动。

    Method for etching integrated circuit structure
    7.
    发明授权
    Method for etching integrated circuit structure 有权
    集成电路结构蚀刻方法

    公开(公告)号:US08124537B2

    公开(公告)日:2012-02-28

    申请号:US12029834

    申请日:2008-02-12

    摘要: A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An O2 plasma etch is performed to etch through the CF-based polymer at the bottom of the trench. The O2 plasma etch has little effect on the SiOCl-based polymer, the thus the upper surfaces of the structure remain covered with polymer. Thus, these upper surfaces remain fully protected during subsequent etching of the layer to be etched.

    摘要翻译: 公开了一种用于蚀刻沟槽内的集成电路结构的方法。 待蚀刻的层被施加在结构之上和沟槽内。 将CF基聚合物沉积在待蚀刻的层上,随后沉积SiOCl基聚合物的覆盖层。 基于CF的聚合物将沟槽的宽度减小到在沟槽底部沉积少量或不存在SiOCl基聚合物的程度。 执行O2等离子体蚀刻以在沟槽的底部蚀刻通过CF基聚合物。 O2等离子体蚀刻对SiOCl基聚合物几乎没有影响,因此结构的上表面保持被聚合物覆盖。 因此,在随后蚀刻待蚀刻的层期间,这些上表面保持完全保护。

    INTEGRATED METHOD OF FABRICATING A MEMORY DEVICE WITH REDUCED PITCH
    8.
    发明申请
    INTEGRATED METHOD OF FABRICATING A MEMORY DEVICE WITH REDUCED PITCH 审中-公开
    一种用减少PITCH制造存储器件的集成方法

    公开(公告)号:US20090035902A1

    公开(公告)日:2009-02-05

    申请号:US11831031

    申请日:2007-07-31

    IPC分类号: H01L21/336

    摘要: Provided is a method of fabricating a memory device. A substrate including an array region and a peripheral region is provided. A first feature and a second feature are formed in the array region. The first feature and the second feature have a first pitch. A plurality of spacers abutting each of the first feature and the second feature are formed. The plurality of spacers have a second pitch. A third feature in the peripheral region and a fourth and fifth feature in the array region are formed concurrently. The forth and fifth feature have the second pitch.

    摘要翻译: 提供一种制造存储器件的方法。 提供了包括阵列区域和外围区域的基板。 第一特征和第二特征形成在阵列区域中。 第一特征和第二特征具有第一音调。 形成邻接第一特征和第二特征的多个间隔件。 多个间隔件具有第二间距。 外围区域的第三特征和阵列区域中的第四和第五特征同时形成。 第四和第五特征具有第二音调。

    SEMICONDUCTOR INTERCONNECT STRUCTURE WITH ROUNDED EDGES AND METHOD FOR FORMING THE SAME
    10.
    发明申请
    SEMICONDUCTOR INTERCONNECT STRUCTURE WITH ROUNDED EDGES AND METHOD FOR FORMING THE SAME 审中-公开
    具有圆形边缘的半导体互连结构及其形成方法

    公开(公告)号:US20080174027A1

    公开(公告)日:2008-07-24

    申请号:US11625527

    申请日:2007-01-22

    IPC分类号: H01L23/48 H01L21/00

    摘要: Provided is a semiconductor interconnect structure formed from an original damascene or dual damascene structure. The original damascene or dual damascene structure includes a planar upper surface consisting of planar upper surfaces of conductive structures formed within openings formed in the dielectric, and planar upper surfaces of the dielectric. The original structure is processed using wet or dry etching operations which, by including ion bombardment and/or ion milling characteristics, both etch the upper dielectric surface and round the upper edges of the originally formed interconnect structures that become exposed as the dielectric is etched. Produced is an interconnect structure within an opening formed in a dielectric and which includes an upper portion that extends above the dielectric and includes opposed upper edges that are rounded.

    摘要翻译: 提供由原始镶嵌或双镶嵌结构形成的半导体互连结构。 原来的镶嵌或双镶嵌结构包括一个平面的上表面,该平面上表面由形成在电介质中形成的开口内的导电结构的平面上表面和电介质的平面上表面组成。 使用湿式或干式蚀刻操作来处理原始结构,其通过包括离子轰击和/或离子研磨特性来蚀刻上电介质表面,并且绕着原始形成的互连结构的上边缘,在电介质被蚀刻时变得暴露。 产生的是在电介质中形成的开口内的互连结构,其包括在电介质上方延伸的上部,并且包括相对的上边缘,其被倒圆。