公开(公告)号：US06417431B1

公开(公告)日：2002-07-09

申请号：US09735133

申请日：2000-12-11

申请人： Clark Wilkinson

发明人： Clark Wilkinson

IPC分类号： G10D316

CPC分类号： G10D3/163

摘要： A guitar pick or plectrum used for playing stringed musical Instruments. The pick has a generally oval triangular configuration. The pick grip pattern consists of a grip at the top of the pick which is a trademark that protrudes above the surface of the pick. The pick also incorporates a circular bevel region surrounding a center hole with a plurality of grip protrusions protruding from the bevel region. The flexibility of the pick may be adjusted by the material injected in a liquid injection mold manufacture process in conjunction with overall pick thickness.

摘要翻译： 用于演奏弦乐器的吉他琴或琴弦。 镐具有大致椭圆形的三角形构造。 拾取手柄图案包括在拾取器顶部的抓握，其是突出在拾取器表面上方的商标。 该拾取还包括围绕中心孔的圆形斜面区域，其具有从斜面区域突出的多个抓握突起。 拾取的灵活性可以通过与液体注射模具制造过程中注入的材料结合整体拾取厚度来调节。

公开(公告)号：US07737723B1

公开(公告)日：2010-06-15

申请号：US12467800

申请日：2009-05-18

申请人： Howard Tang ,  Jack T. Wong ,  Clark Wilkinson ,  Jeffrey S. Byrne

发明人： Howard Tang ,  Jack T. Wong ,  Clark Wilkinson ,  Jeffrey S. Byrne

IPC分类号： H03K19/173

CPC分类号： H03K19/17772 ,  H03K19/17744 ,  H03K19/1776

摘要： In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks adapted to precondition registers within the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.

摘要翻译： 根据本发明的实施例，可编程逻辑器件（PLD，诸如现场可编程门阵列（FPGA））包括多个输入/输出块，其适于在可编程逻辑器件中预处理寄存器，其具有期望的信号值 将输入/输出块的控制释放到由重新配置提供的用户定义的逻辑。

公开(公告)号：US07538574B1

公开(公告)日：2009-05-26

申请号：US11293941

申请日：2005-12-05

申请人： Howard Tang ,  Jack T. Wong ,  Clark Wilkinson ,  Jeffrey S. Byrne

发明人： Howard Tang ,  Jack T. Wong ,  Clark Wilkinson ,  Jeffrey S. Byrne

IPC分类号： H03K19/177

CPC分类号： H03K19/17772 ,  H03K19/17744 ,  H03K19/1776

摘要： In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks having boundary scan cells that are adapted to precondition registers within a logic area of the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.

摘要翻译： 根据本发明的实施例，可编程逻辑器件（PLD，诸如现场可编程门阵列（FPGA））包括具有边界扫描单元的多个输入/输出块，所述边界扫描单元适于预处理逻辑区域内的寄存器 在将输入/输出块的控制释放到由重新配置提供的用户定义的逻辑之前，具有期望信号值的可编程逻辑器件。

公开(公告)号：US08069329B1

公开(公告)日：2011-11-29

申请号：US12021202

申请日：2008-01-28

申请人： Howard Tang ,  Roger Spinti ,  Jeff Byrne ,  Clark Wilkinson

发明人： Howard Tang ,  Roger Spinti ,  Jeff Byrne ,  Clark Wilkinson

IPC分类号： G06F12/00

CPC分类号： H03K19/17752 ,  G06F17/5054 ,  H03K19/17756 ,  H03K19/1776

摘要： Various techniques are described to provide an internally triggered reconfiguration of a programmable logic device (PLD). In one example, a PLD includes configuration memory adapted to store first configuration data to configure the PLD for its intended function. The PLD also includes a bus interface adapted to interface with configuration data storage memory. The PLD further includes user logic configured by the first configuration data and adapted to provide a reconfiguration signal to trigger a reconfiguration of the PLD. In addition, the PLD includes a bus interface controller responsive to the reconfiguration signal for loading second configuration data from the configuration data storage memory via the bus interface.

摘要翻译： 描述了各种技术来提供可编程逻辑器件（PLD）的内部触发的重新配置。 在一个示例中，PLD包括适于存储第一配置数据以配置PLD用于其预期功能的配置存储器。 PLD还包括适于与配置数据存储存储器连接的总线接口。 PLD还包括由第一配置数据配置的用户逻辑，并且适于提供重配置信号以触发PLD的重新配置。 此外，PLD包括响应于重新配置信号的总线接口控制器，用于经由总线接口从配置数据存储存储器加载第二配置数据。