公开(公告)号：US20120128246A1

公开(公告)日：2012-05-24

申请号：US13363209

申请日：2012-01-31

Applicant: Long YANG ,  Julia FAUCHILLE ,  Conrad DANTE ,  Charles Melvin ADEN

Inventor： Long YANG ,  Julia FAUCHILLE ,  Conrad DANTE ,  Charles Melvin ADEN

IPC: G06K9/00

CPC classification number: G06T5/009 ,  G09G5/026 ,  G09G5/10 ,  G09G2320/0626 ,  G09G2320/0666 ,  G09G2320/0673 ,  G09G2340/06 ,  H04N1/6022

Abstract: A method of processing an input image includes receiving an input signal associated with the input image. The input signal includes a plurality of components. The method also includes determining a minimum component of the plurality of components and determining a white signal level as a function of the minimum component. The method further includes multiplying the white signal level by a normalized value computed using a component of the plurality of components to provide a scaled white signal level.

Abstract translation: 处理输入图像的方法包括接收与输入图像相关联的输入信号。 输入信号包括多个分量。 该方法还包括确定多个分量的最小分量并确定作为最小分量的函数的白信号电平。 该方法还包括将白信号电平乘以使用多个分量的分量计算的归一化值以提供缩放的白信号电平。

公开(公告)号：US06812738B1

公开(公告)日：2004-11-02

申请号：US10255656

申请日：2002-09-25

Applicant: Conrad Dante ,  David Lee Rutledge ,  David J. Wicker, Jr.

Inventor： Conrad Dante ,  David Lee Rutledge ,  David J. Wicker, Jr.

IPC: H03K19177

CPC classification number: H03K19/17732 ,  G06F7/49936 ,  G06F7/49994

Abstract: A PLD is disclosed that uses vector routing between components. A vector routing path is coupled between the components and includes a group of wires for routing a group of bits as one vector so that all bits in the vector are switched at once and as a group by a single set of control signals. Vector switch boxes are used to switch entire vectors of a predetermined bit width and a fixed-bit order. The vector routing may be between components in a vector domain, within vector-based components, or between components in a PLD domain and a vector domain. The vector routing path may allow for time-division multiplexing. For example, different components may use the same vector routing path during different time slices. The vector routing path may be dynamically segmented. Dynamic segmentation allows different portions of the same vector routing path to be used simultaneously by different components. A component may be coupled to multiple vector routing paths through a multiplexer. Consequently, the multiplexer may be dynamically switched such that the component receives information from different component sources.

Abstract translation: 公开了在组件之间使用矢量路由的PLD。 矢量路由路径耦合在组件之间，并且包括用于将一组位作为一个向量进行路由的一组线，使得矢量中的所有比特都被一次切换并且通过单组控制信号而被组合。 矢量开关盒用于切换预定位宽和固定位顺序的整个矢量。 矢量路由可以在向量域中的组件之间，基于向量的组件内，或在PLD域和向量域中的组件之间。 矢量路由路径可以允许时分复用。 例如，不同的组件可以在不同的时间片段期间使用相同的向量路由路径。 矢量路由路径可以动态分段。 动态分段允许不同部件同时使用相同矢量路由路径的不同部分。 组件可以通过复用器耦合到多个向量路由路径。 因此，可以动态地切换多路复用器，使得该组件从不同的组件源接收信息。

公开(公告)号：US06907592B1

公开(公告)日：2005-06-14

申请号：US10255474

申请日：2002-09-25

Applicant: Conrad Dante

Inventor： Conrad Dante

IPC: H03K19/177 ,  G06F17/50

CPC classification number: H03K19/17732 ,  G06F7/49936 ,  G06F7/49994

Abstract: A method is disclosed to efficiently route in a programmable logic device (PLD) such as a field-programmable gate array (FPGA). The method includes identifying a source and destination pair in a circuit design; determining multiple candidate paths to route a vector between the source and destination pair; and selecting one of the candidate paths for the vector route. Efficiency may be improved by using time-division multiplexing to route multiple connections through a PLD element.

Abstract translation: 公开了一种在诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）中有效路由的方法。 该方法包括在电路设计中识别源和目的地对; 确定多个候选路径以在源和目的地对之间路由向量; 并选择矢量路由的候选路径之一。 可以通过使用时分复用来通过PLD元件路由多个连接来提高效率。

公开(公告)号：US06844757B2

公开(公告)日：2005-01-18

申请号：US10187236

申请日：2002-06-28

Applicant: Conrad Dante

Inventor： Conrad Dante

IPC: H03K19/177 ,  H03K19/173

CPC classification number: H03K19/17732 ,  G06F7/49936 ,  G06F7/49994

Abstract: A circuit is disclosed for a programmable logic device (PLD) environment that converts unordered bits in a PLD domain to fixed-width vectors in a vector domain. The fixed-width vectors may be used within a vector processing block (VPB) that operates on data in vector format. The PLD includes multiple programmable logic blocks that are configurable by a user. The logic blocks operate on data at a bit level resulting in unordered bits of information in a PLD domain. However, a vector processing block operates on data on a vector level (e.g., 8 bits, 16 bits, 32 bits, 64 bits, etc.). Thus, an interface is coupled between the programmable logic blocks and the vector processing block that converts at least a portion of the unordered bits of information from the PLD domain to one or more fixed-width vectors for use in the vector processing block. The interface may also perform scaling and/or sign extension on the unordered bits, to further free up expensive resources in the PLD domain.

Abstract translation: 公开了一种用于将PLD域中的无序位转换为向量域中的固定宽度向量的可编程逻辑器件（PLD）环境的电路。 可以在对矢量格式的数据进行操作的向量处理块（VPB）内使用固定宽度向量。 PLD包括可由用户配置的多个可编程逻辑块。 逻辑块在位电平上对数据进行操作，导致PLD域中的无序位信息。 然而，向量处理块对矢量级数据（例如，8位，16位，32位，64位等）进行操作。 因此，接口耦合在可编程逻辑块和矢量处理块之间，向量处理块将来自PLD域的信息的无序位的至少一部分转换成用于向量处理块中的一个或多个固定宽度向量。 接口还可以在无序位上执行缩放和/或符号扩展，以进一步释放PLD域中的昂贵资源。

公开(公告)号：US07043511B1

公开(公告)日：2006-05-09

申请号：US10233021

申请日：2002-08-30

Applicant: Conrad Dante

Inventor： Conrad Dante

IPC: G06F7/38

CPC classification number: H03K19/17732 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30072 ,  G06F15/7867

Abstract: A vector-domain engine configured to perform conditional operations on an operand vector in a programmable logic device is disclosed. The vector-domain engine may receive an instruction from and transmit an output vector to a programmable-logic-device domain. The output vector may be a first or second output vector depending on whether a comparison unit in the engine determines that a bit-field of the operand vector matches a designated pattern. The first output vector may be the operand vector modified by a function unit, and the second output vector may be the operand vector unmodified. A shifter may be employed to shift the bit-field to a desired position in the operand vector. The operand vector may comprise a pattern-defining portion and a data portion. The engine may also be configured to test a predetermined number of sequential operand vectors for the presence of the pattern.

Abstract translation: 公开了一种被配置为对可编程逻辑器件中的操作数向量进行条件操作的矢量域引擎。 矢量域引擎可以接收来自可编程逻辑器件域的指令并将其输出到可编程逻辑器件域。 取决于引擎中的比较单元是否确定操作数向量的位域与指定模式匹配，输出向量可以是第一或第二输出向量。 第一输出向量可以是由功能单元修改的操作数向量，并且第二输出向量可以是未修改的操作数向量。 可以使用移位器来将位域移动到操作数向量中的期望位置。 操作数向量可以包括模式定义部分和数据部分。 引擎还可以被配置为测试用于模式存在的预定数量的顺序操作数向量。