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    Reliability test with monitoring of the results
    1.
    发明授权
    Reliability test with monitoring of the results 有权
    可靠性测试与监测结果

    公开(公告)号：US08977513B2

    公开(公告)日：2015-03-10

    申请号：US12904358

    申请日：2010-10-14

    Applicant: Carolina Selva ,  Cosimo Torelli

    Inventor： Carolina Selva ,  Cosimo Torelli

    IPC: G01R31/00 ,  G01R31/3193 ,  G01R31/28

    CPC classification number: G01R31/31935 ,  G01R31/2856

    Abstract: An electronic device for executing a reliability test. Such an electronic device includes a circuit for implementing a functionality of the electronic device, and testing circuit for executing a test of the functional circuit including a plurality of test operations on the functional circuit. The testing circuit returns an indication of a result of each test operation. In an embodiment, the electronic device further includes control circuit for causing the testing circuit to reiterate the test, monitoring circuit for monitoring the result of each test operation to detect a failure of the test operation, and storage circuit for storing failure information indicative of temporal characteristics of each failure.

    Abstract translation: 一种用于执行可靠性测试的电子设备。 这样的电子设备包括用于实现电子设备的功能的电路，以及用于在功能电路上执行包括多个测试操作的功能电路的测试的测试电路。 测试电路返回每个测试操作结果的指示。 在一个实施例中，电子设备还包括控制电路，用于使测试电路重复测试，用于监视每个测试操作的结果以监测测试操作的故障的监视电路，以及存储指示时间的故障信息的存储电路 每个故障的特点。

    RELIABILITY TEST WITH MONITORING OF THE RESULTS
    4.
    发明申请
    RELIABILITY TEST WITH MONITORING OF THE RESULTS 有权
    监测结果的可靠性测试

    公开(公告)号：US20110087453A1

    公开(公告)日：2011-04-14

    申请号：US12904358

    申请日：2010-10-14

    Applicant: Carolina SELVA ,  Cosimo TORELLI

    Inventor： Carolina SELVA ,  Cosimo TORELLI

    IPC: G06F19/00 ,  G01R31/26

    CPC classification number: G01R31/31935 ,  G01R31/2856

    Abstract: An embodiment for executing a reliability test is proposed. A corresponding electronic device includes functional means for implementing a functionality of the electronic device, and testing means for executing a test of the functional means including a plurality of test operations on the functional means; the testing means returns an indication of a result of each test operation. In an embodiment, the electronic device further includes control means for causing the testing means to reiterate the test, monitoring means for monitoring the result of each test operation to detect a failure of the test operation, and storage means for storing failure information indicative of temporal characteristics of each failure.

    Abstract translation: 提出了用于执行可靠性测试的实施例。 相应的电子设备包括用于实现电子设备的功能的功能装置，以及用于执行对功能装置进行多个测试操作的功能装置测试的测试装置; 测试装置返回每个测试操作的结果的指示。 在一个实施例中，电子设备还包括用于使测试装置重复该测试的控制装置，用于监视每个测试操作的结果以检测测试操作失败的监视装置，以及用于存储指示时间的失败信息的存储装置 每个故障的特点。

    Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays
    5.
    发明授权
    Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays 有权
    可编程多模式内置自检和自修复结构的嵌入式存储器阵列

    公开(公告)号：US07284166B2

    公开(公告)日：2007-10-16

    申请号：US11197989

    申请日：2005-08-05

    Applicant: Rita Zappa ,  Carolina Selva ,  Danilo Rimondi ,  Cosimo Torelli

    Inventor： Rita Zappa ,  Carolina Selva ,  Danilo Rimondi ,  Cosimo Torelli

    IPC: G11C29/00

    CPC classification number: G11C29/16 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72

    Abstract: A built-in self-test and self-repair structure (BISR) of memory arrays embedded in an integrated device includes at least a test block (BIST) programmable to execute on a respective memory array of the device any of a certain number of test algorithms, and a self-repair block that includes a column address generator processing the faulty address information for allocating redundant resources of the tested memory array. The BISR may further include a redundancy register on which final redundancy information is loaded at each power-on of the device and control logic for managing data transfer from external circuitry to the built-in self-test and self-repair structure (BISR) and vice versa. The BIST structure serves any number of embedded memory arrays even of different types and sizes.

    Abstract translation: 嵌入在集成设备中的内存阵列的内置自检和自修复结构（BISR）至少包括一个可编程以在设备的相应存储器阵列上执行任意一个测试块的测试块（BIST） 算法和自修复块，其包括处理用于分配被测存储器阵列的冗余资源的故障地址信息的列地址生成器。 BISR可以进一步包括一个冗余寄存器，在该冗余寄存器上加载最终冗余信息，并在该设备的每个上电加载控制逻辑，以及用于管理从外部电路到内部自检和自修复结构（BISR）的数据传输的控制逻辑，以及 反之亦然。 BIST结构即使是不同类型和大小也可用于任何数量的嵌入式存储器阵列。

    Lateral DMOS transistor with first and second drain electrodes in respective contact with high-and low-concentration portions of a drain region
    6.
    发明授权
    Lateral DMOS transistor with first and second drain electrodes in respective contact with high-and low-concentration portions of a drain region 有权
    具有第一和第二漏电极的横向DMOS晶体管分别与漏区的高浓度和低浓度部分接触

    公开(公告)号：US06624471B2

    公开(公告)日：2003-09-23

    申请号：US09960254

    申请日：2001-09-20

    Applicant: Nicola Zatelli ,  Massimo Atti ,  Elisabetta Palumbo ,  Cosimo Torelli

    Inventor： Nicola Zatelli ,  Massimo Atti ,  Elisabetta Palumbo ,  Cosimo Torelli

    IPC: H01L2976

    CPC classification number: H01L29/41725 ,  H01L29/7835

    Abstract: A lateral DMOS transistor having a drain region which comprises a high-concentration portion with which the drain electrode is in contact and a low-concentration portion which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode in contact with a point of the low-concentration portion of the drain region which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

    Abstract translation: 一种具有漏极区域的横向DMOS晶体管，其包括漏电极接触的高浓度部分和由沟道区域限定的低浓度部分。 除了常规的源极，漏极，体和栅电极之外，晶体管还具有与漏极区域的靠近沟道的低浓度部分的点接触的附加电极。 附加电极允许直接测量栅极电介质中的电场，并且因此提供可以用于表征晶体管并选择其尺寸的信息，并且用于激活用于保护晶体管和/或其中包含的集成电路的其它部件的器件 晶体管。

    REDUCTION OF POWER CONSUMPTION OF AN INTEGRATED ELECTRONIC SYSTEM COMPRISING DISTINCT STATIC RANDOM ACCESS RESOURCES FOR STORING DATA
    7.
    发明申请
    REDUCTION OF POWER CONSUMPTION OF AN INTEGRATED ELECTRONIC SYSTEM COMPRISING DISTINCT STATIC RANDOM ACCESS RESOURCES FOR STORING DATA 审中-公开
    减少包含静态随机存取资源存储数据的集成电子系统的功耗

    公开(公告)号：US20080151675A1

    公开(公告)日：2008-06-26

    申请号：US11963145

    申请日：2007-12-21

    Applicant: Cosimo Torelli ,  Danilo Rimondi ,  Rita Zappa

    Inventor： Cosimo Torelli ,  Danilo Rimondi ,  Rita Zappa

    IPC: G11C5/14

    CPC classification number: G11C5/14 ,  G11C11/417

    Abstract: An integrated circuit includes an array of memory cells arranged in a plurality of sectors. Each sector includes a plurality of distinct random access memory resources able to be accessed differently in different modes. Peripheral circuitry is commonly shared by at least some of the sectors for addressing and reading/writing data. A respective dedicated controllable power supply line is coupled to each sector.

    Abstract translation: 集成电路包括布置在多个扇区中的存储单元的阵列。 每个扇区包括能够以不同模式被不同地访问的多个不同的随机存取存储器资源。 外围电路通常由用于寻址和读取/写入数据的至少一些扇区共享。 相应的专用可控电源线连接到每个扇区。

    Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays
    8.
    发明申请
    Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays 有权
    可编程多模式内置自检和自修复结构的嵌入式存储器阵列

    公开(公告)号：US20060031726A1

    公开(公告)日：2006-02-09

    申请号：US11197989

    申请日：2005-08-05

    Applicant: Rita Zappa ,  Carolina Selva ,  Danilo Rimondi ,  Cosimo Torelli

    Inventor： Rita Zappa ,  Carolina Selva ,  Danilo Rimondi ,  Cosimo Torelli

    IPC: G11C29/00

    CPC classification number: G11C29/16 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72

    Abstract: A built-in self-test and self-repair structure (BISR) of memory arrays embedded in an integrated device includes at least a test block (BIST) programmable to execute on a respective memory array of the device any of a certain number of test algorithms, and a self-repair block that includes a column address generator processing the faulty address information for allocating redundant resources of the tested memory array. The BISR may further include a redundancy register on which final redundancy information is loaded at each power-on of the device and control logic for managing data transfer from external circuitry to the built-in self-test and self-repair structure (BISR) and vice versa. The BIST structure serves any number of embedded memory arrays even of different types and sizes.

    Abstract translation: 嵌入在集成设备中的内存阵列的内置自检和自修复结构（BISR）至少包括一个可编程以在设备的相应存储器阵列上执行任意一个测试块的测试块（BIST） 算法和自修复块，其包括处理用于分配被测存储器阵列的冗余资源的故障地址信息的列地址生成器。 BISR可以进一步包括一个冗余寄存器，在该冗余寄存器上加载最终冗余信息，并在该设备的每个上电加载控制逻辑，以及用于管理从外部电路到内部自检和自修复结构（BISR）的数据传输的控制逻辑，以及 反之亦然。 BIST结构即使是不同类型和大小也可用于任何数量的嵌入式存储器阵列。

    Process and system for the verification of correct functioning of an on-chip memory
    9.
    发明授权
    Process and system for the verification of correct functioning of an on-chip memory 有权
    用于验证片上存储器正确功能的过程和系统

    公开(公告)号：US08161327B2

    公开(公告)日：2012-04-17

    申请号：US12101711

    申请日：2008-04-11

    Applicant: Carolina Selva ,  Cosimo Torelli ,  Danilo Rimondi ,  Rita Zappa

    Inventor： Carolina Selva ,  Cosimo Torelli ,  Danilo Rimondi ,  Rita Zappa

    IPC: G06F11/00

    CPC classification number: G01R31/3187 ,  G06F11/1004 ,  G11C17/14 ,  G11C29/40 ,  G11C2029/0401 ,  G11C2029/4402

    Abstract: A method is for making an integrated circuit with built-in self-test. The method includes forming at least one nonvolatile read only memory (ROM) to store ROM code and forming a logic self-test circuit to verify a correct functioning of the at least one nonvolatile ROM. Moreover, the method includes defining, in the logic self-test circuit, a logic self-test core to process the ROM code and to generate a flag based upon a control signature and defining, in the logic self-test circuit, a nonvolatile storage block, coupled to the logic self-test core, to store the control signature. Furthermore, the method includes writing the ROM code to the at least one nonvolatile ROM and writing the control signature to the nonvolatile storage block, during a same fabrication step.

    Abstract translation: 一种用于制作具有内置自检功能的集成电路的方法。 该方法包括形成至少一个非易失性只读存储器（ROM）以存储ROM代码并形成逻辑自检电路以验证至少一个非易失性ROM的正确功能。 此外，该方法包括在逻辑自检电路中定义逻辑自测核心以处理ROM代码并基于控制签名生成标志，并在逻辑自测电路中定义非易失性存储器 块，耦合到逻辑自检核心，存储控制签名。 此外，该方法包括在相同的制造步骤期间将ROM代码写入至少一个非易失性ROM并将控制签名写入非易失性存储块。

    PROCESS AND SYSTEM FOR THE VERIFICATION OF CORRECT FUNCTIONING OF AN ON-CHIP MEMORY
    10.
    发明申请
    PROCESS AND SYSTEM FOR THE VERIFICATION OF CORRECT FUNCTIONING OF AN ON-CHIP MEMORY 有权
    验证片上存储器正确功能的过程和系统

    公开(公告)号：US20080256407A1

    公开(公告)日：2008-10-16

    申请号：US12101711

    申请日：2008-04-11

    Applicant: Carolina Selva ,  Cosimo Torelli ,  Danilo Rimondi ,  Rita Zappa

    Inventor： Carolina Selva ,  Cosimo Torelli ,  Danilo Rimondi ,  Rita Zappa

    IPC: G01R31/3187 ,  G06F11/27

    CPC classification number: G01R31/3187 ,  G06F11/1004 ,  G11C17/14 ,  G11C29/40 ,  G11C2029/0401 ,  G11C2029/4402

    Abstract: A method is for making an integrated circuit with built-in self-test. The method includes forming at least one nonvolatile read only memory (ROM) to store ROM code and forming a logic self-test circuit to verify a correct functioning of the at least one nonvolatile ROM. Moreover, the method includes defining, in the logic self-test circuit, a logic self-test core to process the ROM code and to generate a flag based upon a control signature and defining, in the logic self-test circuit, a nonvolatile storage block, coupled to the logic self-test core, to store the control signature. Furthermore, the method includes writing the ROM code to the at least one nonvolatile ROM and writing the control signature to the nonvolatile storage block, during a same fabrication step.

    Abstract translation: 一种用于制作具有内置自检功能的集成电路的方法。 该方法包括形成至少一个非易失性只读存储器（ROM）以存储ROM代码并形成逻辑自检电路以验证至少一个非易失性ROM的正确功能。 此外，该方法包括在逻辑自检电路中定义逻辑自测核心以处理ROM代码并基于控制签名生成标志，并在逻辑自测电路中定义非易失性存储器 块，耦合到逻辑自检核心，存储控制签名。 此外，该方法包括在相同的制造步骤期间将ROM代码写入至少一个非易失性ROM并将控制签名写入非易失性存储块。

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