公开(公告)号：US08084769B2

公开(公告)日：2011-12-27

申请号：US11675635

申请日：2007-02-16

申请人： Shyh-Fann Ting ,  Sheng-Hao Lin ,  Chien-Hsing Lee ,  Da-Ching Chiou ,  Sun-Chin Wei ,  Min-Yi Chang ,  Cheng-Tung Huang ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng

发明人： Shyh-Fann Ting ,  Sheng-Hao Lin ,  Chien-Hsing Lee ,  Da-Ching Chiou ,  Sun-Chin Wei ,  Min-Yi Chang ,  Cheng-Tung Huang ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng

IPC分类号： H01L23/544 ,  H01L21/66

CPC分类号： H01L22/34

摘要： A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction.

摘要翻译： 测试键设计模式包括至少一个导电触点，垂直并电连接到导电触点的至少一个第一宽度的导线和分别直接连接到导线的每一侧的至少一对源极和漏极。 一对源极和漏极以及直接连接到源极和漏极的第一长度的导电线的一部分形成电子器件。 测试键设计模式在测量电容时具有较小误差和更好的栅极氧化物厚度提取的优势。

公开(公告)号：US20080197351A1

公开(公告)日：2008-08-21

申请号：US11675635

申请日：2007-02-16

申请人： Shyh-Fann Ting ,  Sheng-Hao Lin ,  Chien-Hsing Lee ,  Da- Ching Chiou ,  Sun-Chin Wei ,  Min-Yi Chang ,  Cheng-Tung Huang ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng

发明人： Shyh-Fann Ting ,  Sheng-Hao Lin ,  Chien-Hsing Lee ,  Da- Ching Chiou ,  Sun-Chin Wei ,  Min-Yi Chang ,  Cheng-Tung Huang ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng

IPC分类号： H01L23/58

CPC分类号： H01L22/34

摘要： A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction.

摘要翻译： 测试键设计模式包括至少一个导电触点，垂直并电连接到导电触点的至少一个第一宽度的导线和分别直接连接到导线的每一侧的至少一对源极和漏极。 一对源极和漏极以及直接连接到源极和漏极的第一长度的导电线的一部分形成电子器件。 测试键设计模式在测量电容时具有较小误差和更好的栅极氧化物厚度提取的优势。

公开(公告)号：US20070275530A1

公开(公告)日：2007-11-29

申请号：US11308899

申请日：2006-05-24

申请人： Wen-Han Hung ,  Cheng-Tung Huang ,  Da-Ching Chiou ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzermin Shen ,  Tzyy-Ming Cheng

发明人： Wen-Han Hung ,  Cheng-Tung Huang ,  Da-Ching Chiou ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzermin Shen ,  Tzyy-Ming Cheng

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L29/665 ,  H01L29/6653

摘要： A semiconductor structure and a method of fabricating the same are provided. A substrate having a metal-oxide-semiconductor transistor is provided. The metal-oxide-semiconductor transistor includes a gate, a source/drain extended region, a first spacer, a liner, a source/drain and a metal silicide layer. A portion of the first spacer is removed to form a second spacer by performing an etching process. A contact etching stop layer is formed over the substrate.

摘要翻译： 提供半导体结构及其制造方法。 提供具有金属氧化物半导体晶体管的衬底。 金属氧化物半导体晶体管包括栅极，源极/漏极延伸区域，第一间隔物，衬垫，源极/漏极和金属硅化物层。 通过进行蚀刻处理，去除第一间隔物的一部分以形成第二间隔物。 接触蚀刻停止层形成在衬底上。