公开(公告)号：US20130002375A1

公开(公告)日：2013-01-03

申请号：US13175253

申请日：2011-07-01

申请人： Ming-Tzong Yang ,  Tung-Hsing Lee ,  Kuei-Ti Chan

发明人： Ming-Tzong Yang ,  Tung-Hsing Lee ,  Kuei-Ti Chan

IPC分类号： H01P3/08

CPC分类号： H01L23/5225 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transmission line structure is disclosed. The structure includes at least one signal transmission line and a pair of ground transmission lines embedded in a first level of a dielectric layer on a substrate, wherein the pair of ground transmission lines are on both sides of the signal transmission line. A first ground layer is embedded in a second level lower than the first level of the dielectric layer and a second ground layer is embedded in a third level higher than the first level of the dielectric layer. First and second pairs of via connectors are embedded in the dielectric layer, wherein the first pair of via connectors electrically connects the pair of ground transmission lines to the first ground layer and the second pair of via connectors electrically connects the pair of ground transmission lines to the second ground layer.

摘要翻译： 公开了传输线结构。 该结构包括至少一个信号传输线和嵌入在基板上的电介质层的第一层中的一对接地传输线，其中该对接地传输线位于信号传输线的两侧。 第一接地层嵌入在比电介质层的第一电平低的第二电平中，并且第二接地层嵌入在比电介质层的第一电平高的第三电平中。 第一对和第二对通孔连接器嵌入在电介质层中，其中第一对通孔连接器将一对接地传输线电连接到第一接地层，而第二对通孔连接器将一对接地传输线电连接到 第二层地层。

公开(公告)号：US20130001734A1

公开(公告)日：2013-01-03

申请号：US13175230

申请日：2011-07-01

申请人： Ming-Tzong Yang ,  Tung-Hsing Lee

发明人： Ming-Tzong Yang ,  Tung-Hsing Lee

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0649 ,  H01L29/0692

摘要： A Schottky diode structure includes a semiconductor substrate having an anode region and a cathode region. A lightly doped region with a predetermined conductivity type is in the semiconductor substrate. A metal contact overlies the lightly doped region and corresponds to the cathode region to serve as a cathode. A metal silicide layer is beneath and electrically connected to the metal contact, wherein the metal silicide layer, directly under the metal contact, is in direct contact with the lightly doped region. A heavily doped region with the predetermined conductivity type is in the lightly doped region and corresponds to the anode region to serve as an anode.

摘要翻译： 肖特基二极管结构包括具有阳极区域和阴极区域的半导体衬底。 具有预定导电类型的轻掺杂区域在半导体衬底中。 金属接触覆盖轻掺杂区域，并且对应于阴极区域以用作阴极。 金属硅化物层在金属接触下方并电连接，金属硅化物层直接在金属接触下方与轻掺杂区直接接触。 具有预定导电类型的重掺杂区域在轻掺杂区域中，并且对应于用作阳极的阳极区域。

公开(公告)号：US20120313217A1

公开(公告)日：2012-12-13

申请号：US13351151

申请日：2012-01-16

申请人： Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Yu-Hua HUANG ,  Ming-Tzong YANG

发明人： Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Yu-Hua HUANG ,  Ming-Tzong YANG

IPC分类号： H01L29/92

CPC分类号： H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/0805 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate of a conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. A capacitor is disposed under the seal ring structure and is electrically connected thereto, wherein the capacitor includes a body of the semiconductor substrate.

摘要翻译： 公开了一种半导体器件。 该半导体器件包括具有由密封环区域包围的芯片区域的导电类型的半导体衬底。 绝缘层位于半导体衬底上。 密封环结构埋设在对应于密封圈区域的绝缘层中。 电容器设置在密封环结构下方并与其电连接，其中电容器包括半导体衬底的主体。

公开(公告)号：US08188578B2

公开(公告)日：2012-05-29

申请号：US12273552

申请日：2008-11-19

申请人： Tung-Hsing Lee ,  Tien-Chang Chang ,  Yuan-Hung Chung

发明人： Tung-Hsing Lee ,  Tien-Chang Chang ,  Yuan-Hung Chung

IPC分类号： H01L23/552 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L31/00 ,  H01L23/58 ,  H01L29/06

CPC分类号： H01L23/5225 ,  H01L23/552 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A seal ring structure disposed along a periphery of an integrated circuit. The seal ring is divided into at least a first portion and a second portion. The second portion is positioned facing and shielding an analog and/or RF circuit block from a noise. A deep N well is disposed in a P substrate and is positioned under the second portion. The deep N well reduces the substrate noise coupling.

摘要翻译： 沿着集成电路的周边设置的密封环结构。 密封环被分成至少第一部分和第二部分。 第二部分定位成面对并屏蔽模拟和/或RF电路块免受噪音。 深N阱设置在P基板中并且位于第二部分下方。 深N阱降低了衬底噪声耦合。

公开(公告)号：US20110133308A1

公开(公告)日：2011-06-09

申请号：US13029066

申请日：2011-02-16

申请人： Kuei-Ti Chan ,  Tung-Hsing Lee ,  Augusto Marques ,  Wen-Chang Lee

发明人： Kuei-Ti Chan ,  Tung-Hsing Lee ,  Augusto Marques ,  Wen-Chang Lee

IPC分类号： H01L29/86

CPC分类号： H01L28/10 ,  H01L21/76229 ,  H01L27/0207 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate; an inductor wiring pattern overlying the substrate, wherein the inductor wiring pattern is formed in an inductor-forming region; a plurality of shielding patterns between the inductor wiring pattern and the substrate within the inductor-forming region; and at least one first oxide define (OD) pattern disposed in the substrate or between the inductor wiring pattern and the substrate.

摘要翻译： 半导体器件包括衬底; 覆盖所述基板的电感器布线图案，其中所述电感器布线图案形成在电感器形成区域中; 在电感器形成区域内的电感器布线图案和基板之间的多个屏蔽图案; 并且至少一个第一氧化物限定（OD）图案设置在基板中或电感器布线图案和基板之间。

公开(公告)号：US20110037121A1

公开(公告)日：2011-02-17

申请号：US12541967

申请日：2009-08-16

申请人： Tung-Hsing Lee ,  I-Cheng Lin ,  Wei-Li Tsao

发明人： Tung-Hsing Lee ,  I-Cheng Lin ,  Wei-Li Tsao

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L29/7835 ,  H01L27/0266 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66659

摘要： An I/O electrostatic discharge (ESD) device having a gate electrode over a substrate, a gate dielectric layer between the gate electrode and the substrate, a pair of sidewall spacers respectively disposed on two opposite sidewalls of the gate electrode, a first lightly doped drain (LDD) region disposed under one of the sidewall spacers, a source region disposed next to the first LDD region, a second LDD region disposed under the other sidewall spacer, and a drain region disposed next to the second LDD region, wherein a doping concentration of the second LDD region is larger than a doping concentration of the first LDD region.

摘要翻译： 一种在衬底上具有栅电极的I / O静电放电（ESD）器件，在栅电极和衬底之间的栅极电介质层，分别设置在栅电极的两个相对侧壁上的一对侧壁间隔物，第一轻掺杂 漏极（LDD）区域，设置在所述侧壁间隔件之一之下，源区域设置在所述第一LDD区域旁边，设置在所述另一侧壁间隔物下方的第二LDD区域和设置在所述第二LDD区域旁边的漏极区域， 第二LDD区域的浓度大于第一LDD区域的掺杂浓度。

公开(公告)号：US20100213504A1

公开(公告)日：2010-08-26

申请号：US12389378

申请日：2009-02-20

申请人： Ching-Chung Ko ,  Tung-Hsing Lee

发明人： Ching-Chung Ko ,  Tung-Hsing Lee

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/735

摘要： A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

摘要翻译： 横向双极结晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 以及围绕所述基底区域的收集器区域; 其中所述栅极下方的所述基极区域的所述部分未经过阈值电压注入工艺。

公开(公告)号：US20090261937A1

公开(公告)日：2009-10-22

申请号：US12493245

申请日：2009-06-29

申请人： Ching-Chung Ko ,  Tung-Hsing Lee ,  Kuei-Ti Chan ,  Tao Cheng ,  Ming-Tzong Yang

发明人： Ching-Chung Ko ,  Tung-Hsing Lee ,  Kuei-Ti Chan ,  Tao Cheng ,  Ming-Tzong Yang

IPC分类号： H01F5/00

CPC分类号： H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well.

摘要翻译： 集成电感器包括由钝化层顶部的铝层组成的绕组，其中铝层不延伸到钝化层中，并且具有不小于约2.0微米的厚度。 钝化层的厚度不小于约0.8微米。 通过从集成电感器中消除铜并增加钝化层的厚度，电感器结构的底表面与半导体衬底的主表面之间的距离增加，因此寄生衬底耦合可能会降低，Q因子 可以改进。 此外，铝层的增加的厚度也可以有助于改善Q因子。

公开(公告)号：US07294541B2

公开(公告)日：2007-11-13

申请号：US11163470

申请日：2005-10-20

申请人： Li-Shian Jeng ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng ,  Tzermin Shen ,  Da-Ching Cho

发明人： Li-Shian Jeng ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng ,  Tzermin Shen ,  Da-Ching Cho

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/324 ,  H01L21/28167 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of fabricating a gate dielectric layer is described. First, a well is produced in a substrate. Later, the substrate is cleaned. Then the substrate is processed by a pre-annealed process. Afterwards, a gate dielectric layer is formed on the substrate. As a result, the on-current of the semiconductor device can be increased.

摘要翻译： 描述了制造栅介质层的方法。 首先，在底物中产生孔。 之后，清洗基板。 然后通过预退火工艺处理衬底。 之后，在基板上形成栅介质层。 结果，可以提高半导体器件的导通电流。

公开(公告)号：US20060040448A1

公开(公告)日：2006-02-23

申请号：US10711038

申请日：2004-08-19

申请人： Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

发明人： Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

IPC分类号： H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/6659

摘要： The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to form a shallow-junction doping region of a first conductive type in the substrate next to each of the sidewalls of the first gate structure, followed by the formation of offset spacers on each of the sidewalls of the first and second gate structure. A second ion implantation process is performed to form a shallow-junction doping region of a second conductive type in the substrate next to the offset spacer on each of the sidewalls of the second gate structure.

摘要翻译： 本发明公开了一种半导体器件的制造方法。 提供基板。 具有侧壁的至少一个第一和第二栅极结构被包括在基板的表面上。 执行第一离子注入工艺以在基板中的第一栅极结构的每个侧壁旁边形成第一导电类型的浅结掺杂区域，随后在第一栅极结构的每个侧壁上形成偏置间隔物 和第二门结构。 执行第二离子注入工艺以在第二栅极结构的每个侧壁上的偏移间隔物旁边的衬底中形成第二导电类型的浅结掺杂区域。