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公开(公告)号：US5313520A
公开(公告)日：1994-05-17
申请号：US11105
申请日：1993-01-29
申请人： Dae K. Han
发明人： Dae K. Han
CPC分类号： G06F12/1466
摘要： A method and a device are provided for protecting data stored in a ROM of a micoprogram control unit. Such data may take the form of a user program. To protect the data, predetermined code data is written into a predetermined address in the ROM. A code address inputted from outside the microprogram control unit is then compared with the predetermined address. If the inputted code address is determined to match the predetermined address, then code data inputted from outside the microprogram control unit is compared with the predetermined code data. Only after both of these comparisons are successfully made is the data in the ROM allowed to be read outside the microprogram control unit.
摘要翻译： 提供了一种用于保护存储在微控制单元的ROM中的数据的方法和装置。 这样的数据可以采取用户程序的形式。 为了保护数据，将预定码数据写入ROM中的预定地址。 然后将从微程序控制单元外部输入的代码地址与预定地址进行比较。 如果确定输入的代码地址与预定地址相匹配，则从微程序控制单元外部输入的代码数据与预定代码数据进行比较。 只有在两次比较成功之后，才允许在微程序控制单元之外读取ROM中的数据。
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公开(公告)号：US5363406A
公开(公告)日：1994-11-08
申请号：US112281
申请日：1993-08-27
申请人： Dae K. Han
发明人： Dae K. Han
CPC分类号： G06F1/025
摘要： A pulse width modulation apparatus having a storage circuit for temporarily storing pulse width data inputted over a data bus and then inverting it, the pulse width data determining a pulse width, a counting circuit for counting a clock signal in response to an external pulse width modulation enable signal and an external reset signal, a comparison circuit for comparing the number of logical 0 bits of the inverted pulse width data from the storage circuit with the number of logical 1 bits of count data from the counting circuit and outputting a high signal when the number of the logical 0 bits of the inverted pulse width data is greater than or equal to the number of the logical 1 bits of the count data and a low signal when the number of the logical 0 bits of the inverted pulse width data is smaller than the number of the logical 1 bits of the count data, and an output circuit for latching an output signal from the comparison circuit to output a pulse width modulation signal. Therefore, since the comparison of the pulse width data and the count data are performed only with PMOS and NMOS transistors of different current gains in the comparison circuit, the processing time can be reduced and the integration can be enhanced in manufacturing a single chip.
摘要翻译： 一种脉宽调制装置，具有存储电路，用于临时存储在数据总线上输入的脉冲宽度数据，然后使其反相，脉冲宽度数据确定脉冲宽度;计数电路，用于响应外部脉冲宽度调制对时钟信号进行计数 使能信号和外部复位信号，比较电路，用于将来自存储电路的反相脉冲宽度数据的逻辑0位数与来自计数电路的计数数据的逻辑1位数进行比较，当输出高信号时 反转脉冲宽度数据的逻辑0比特数大于或等于计数数据的逻辑1比特数，而当反相脉冲宽度数据的逻辑0比特数小于 计数数据的逻辑1位数，以及用于锁存来自比较电路的输出信号以输出脉宽调制信号的输出电路。 因此，由于脉冲宽度数据和计数数据的比较仅在比较电路中仅利用不同电流增益的PMOS晶体管和NMOS晶体管进行，所以可以减少处理时间并且可以在制造单个芯片时提高集成度。
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公开(公告)号：US5305003A
公开(公告)日：1994-04-19
申请号：US880772
申请日：1992-05-11
申请人： Dae K. Han
发明人： Dae K. Han
CPC分类号： H03M1/1071 , H03M1/12
摘要： A test device of an A/D converter contained in a one-chip microcomputer capable of testing all failures in a digital part of the A/D converter by testing the digital part at a function test step carried out by the microcomputer. The test device comprises an A/D test load register for storing a digital value corresponding to an analog value to be tested. In an A/D self-test mode, data from the A/D test load register is stored in an A/D data register via a control logic, upon setting of an A/D start flag. Storing of the data is achieved, in place of an output from a comparator based on an analog input signal. As the data is read, it is possible to test analog and digital parts of the A/D converter individually, at a function test step, thereby verifying all failures in the A/D converter.
摘要翻译： 一种A / D转换器的测试装置，其包含在能够通过在由微计算机执行的功能测试步骤下测试数字部分来测试A / D转换器的数字部分中的所有故障的单片微计算机。 测试装置包括用于存储与要测试的模拟值对应的数字值的A / D测试加载寄存器。 在A / D自检模式下，A / D测试加载寄存器的数据通过A / D开始标志的设置通过控制逻辑存储在A / D数据寄存器中。 实现数据的存储，代替来自基于模拟输入信号的比较器的输出。 随着读取数据，可以在功能测试步骤中单独测试A / D转换器的模拟和数字部分，从而验证A / D转换器中的所有故障。
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