公开(公告)号：US07368373B2

公开(公告)日：2008-05-06

申请号：US11162081

申请日：2005-08-29

申请人： Min-San Huang ,  Dah-Chuan Chen ,  Rex Young

发明人： Min-San Huang ,  Dah-Chuan Chen ,  Rex Young

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L29/42328 ,  H01L29/66825

摘要： A method for manufacturing a semiconductor device is disclosed suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent to the first conductive structure. Then, the size of the second conductive structure is reduced so that a top surface of the second conductive structure is relatively lower than that of the first conductive structure. Thereafter, a second dielectric layer is formed over the substrate to cover the first and the second conductive structure. A via is formed in the second dielectric layer to expose the top surface of the first conductive structure. Finally, a via plug is formed in the via.

摘要翻译： 公开了一种用于制造半导体器件的方法，其适用于具有第一导电结构和第一介电层的衬底，其中介电层覆盖第一导电结构。 该方法包括以下步骤：在与第一导电结构相邻的衬底上形成第二导电结构。 然后，第二导电结构的尺寸减小，使得第二导电结构的顶表面相对低于第一导电结构的顶表面。 此后，在衬底上形成第二电介质层以覆盖第一和第二导电结构。 在第二电介质层中形成通孔以露出第一导电结构的顶表面。 最后，在通孔中形成通孔塞。

公开(公告)号：US20060211204A1

公开(公告)日：2006-09-21

申请号：US11163858

申请日：2005-11-01

申请人： Min-San Huang ,  Dah-Chuan Chen ,  Liang-Chuan Lai

发明人： Min-San Huang ,  Dah-Chuan Chen ,  Liang-Chuan Lai

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L29/40114 ,  H01L29/66825

摘要： A method for fabricating a non-volatile memory is disclosed. First, a semiconductor device is formed in a substrate, and the top of the semiconductor device is higher than the surface of the substrate. Then, a first dielectric layer is formed on the substrate, and the first dielectric layer covers the semiconductor device and the substrate. A portion of the first dielectric layer is removed so as to retain a portion of the first dielectric layer on the sidewall of the semiconductor device and the substrate. Afterwards, a second dielectric layer and a conductive layer are sequentially formed on the substrate, and a corresponding pair of mask spacers is formed on the conductive layer disposed on the sidewall of the semiconductor device. Finally, the mask spacers are used as an etching mask to continuously etch a portion of the conductive layer until the surface of the second dielectric layer is exposed.

摘要翻译： 公开了一种用于制造非易失性存储器的方法。 首先，在衬底中形成半导体器件，并且半导体器件的顶部高于衬底的表面。 然后，在基板上形成第一电介质层，第一电介质层覆盖半导体器件和基板。 去除第一电介质层的一部分，以便将第一电介质层的一部分保持在半导体器件和衬底的侧壁上。 之后，在衬底上依次形成第二电介质层和导电层，并且在设置在半导体器件的侧壁上的导电层上形成相应的一对掩模间隔物。 最后，将掩模间隔物用作蚀刻掩模，以连续蚀刻导电层的一部分，直到第二介电层的表面露出。

公开(公告)号：US20060183311A1

公开(公告)日：2006-08-17

申请号：US11162081

申请日：2005-08-29

申请人： Min-San Huang ,  Dah-Chuan Chen ,  Rex Young

发明人： Min-San Huang ,  Dah-Chuan Chen ,  Rex Young

IPC分类号： H01L21/44

CPC分类号： H01L21/76897 ,  H01L29/42328 ,  H01L29/66825

摘要： A method for manufacturing a semiconductor device is disclosed suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent to the first conductive structure. Then, the size of the second conductive structure is reduced so that a top surface of the second conductive structure is relatively lower than that of the first conductive structure. Thereafter, a second dielectric layer is formed over the substrate to cover the first and the second conductive structure. A via is formed in the second dielectric layer to expose the top surface of the first conductive structure. Finally, a via plug is formed in the via.

摘要翻译： 公开了一种用于制造半导体器件的方法，其适用于具有第一导电结构和第一介电层的衬底，其中介电层覆盖第一导电结构。 该方法包括以下步骤：在与第一导电结构相邻的衬底上形成第二导电结构。 然后，第二导电结构的尺寸减小，使得第二导电结构的顶表面相对低于第一导电结构的顶表面。 此后，在衬底上形成第二电介质层以覆盖第一和第二导电结构。 在第二电介质层中形成通孔以露出第一导电结构的顶表面。 最后，在通孔中形成通孔塞。

公开(公告)号：US20080153289A1

公开(公告)日：2008-06-26

申请号：US12041676

申请日：2008-03-04

申请人： Min-San Huang ,  Dah-Chuan Chen ,  Rex Young

发明人： Min-San Huang ,  Dah-Chuan Chen ,  Rex Young

IPC分类号： H01L21/768

CPC分类号： H01L21/76897 ,  H01L29/42328 ,  H01L29/66825

摘要： A method for manufacturing a semiconductor device is disclosed. The method is suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent to the first conductive structure. Then, the size of the second conductive structure is reduced so that a top surface of the second conductive structure is relatively lower than that of the first conductive structure. Thereafter, a second dielectric layer is formed over the substrate to cover the first and the second conductive structure. A via is formed in the second dielectric layer to expose the top surface of the first conductive structure. Finally, a via plug is formed in the via.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法适用于具有第一导电结构和第一介电层的基板，其中介电层覆盖第一导电结构。 该方法包括以下步骤：在与第一导电结构相邻的衬底上形成第二导电结构。 然后，第二导电结构的尺寸减小，使得第二导电结构的顶表面相对低于第一导电结构的顶表面。 此后，在衬底上形成第二电介质层以覆盖第一和第二导电结构。 在第二电介质层中形成通孔以露出第一导电结构的顶表面。 最后，在通孔中形成通孔塞。

公开(公告)号：US07309632B1

公开(公告)日：2007-12-18

申请号：US11735440

申请日：2007-04-14

申请人： Wei-Bo Lu ,  Dah-Chuan Chen

发明人： Wei-Bo Lu ,  Dah-Chuan Chen

IPC分类号： H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11517 ,  H01L27/11521

摘要： A method of fabricating a nonvolatile memory cell includes providing a substrate with a trench, with a sidewall where a tunnel oxide layer and a floating gate are successively formed, forming a control gate in the trench, performing a high density plasma deposition process to form an HDP oxide layer on the top surface of control gate.

摘要翻译： 一种制造非易失性存储单元的方法包括提供具有沟槽的衬底，其中连续形成隧道氧化物层和浮栅的侧壁，在沟槽中形成控制栅极，执行高密度等离子体沉积工艺以形成 HDP氧化层在控制门的顶面。