公开(公告)号：US20090230515A1

公开(公告)日：2009-09-17

申请号：US12399649

申请日：2009-03-06

申请人： Syouji MIYAHARA ,  Daichi SUMA

发明人： Syouji MIYAHARA ,  Daichi SUMA

IPC分类号： H01L29/41 ,  H01L21/22

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811

摘要： A well region in which an insulated gate semiconductor element is formed is a diffusion region, and an impurity concentration of the well region is lower toward its bottom portion. This leads to a problem of increased resistance. Therefore, particularly, an insulated gate semiconductor element having an up-drain structure has a problem of increased on-resistance. A p type well region is formed by stacking two p type impurity regions on one another. The p type impurity regions are allowed to serve as the p type well region by sequentially stacking n type semiconductor layers, on one another, having p type impurities implanted into their surfaces and simultaneously diffusing the impurities by heat treatment. In this way, it is possible to obtain the p type well region in which an impurity concentration sufficient to secure a desired breakdown voltage is maintained approximately uniform up to a desired depth.

摘要翻译： 其中形成绝缘栅极半导体元件的阱区是扩散区，并且阱区的杂质浓度朝向其底部较低。 这导致阻力增加的问题。 因此，特别地，具有上溢结构的绝缘栅半导体元件具有导通电阻增加的问题。 p型阱区通过彼此堆叠两个p型杂质区而形成。 通过依次堆叠n型半导体层，将p型杂质注入其表面并同时通过热处理扩散杂质，使p型杂质区域用作p型阱区。 以这种方式，可以获得其中足以确保所需击穿电压的杂质浓度保持大致均匀至所需深度的p型阱区。

公开(公告)号：US20060071239A1

公开(公告)日：2006-04-06

申请号：US11237834

申请日：2005-09-29

申请人： Koichi Saito ,  Yoshikazu Ibara ,  Tatsuhiko Koide ,  Daichi Suma

发明人： Koichi Saito ,  Yoshikazu Ibara ,  Tatsuhiko Koide ,  Daichi Suma

IPC分类号： H01L31/0328 ,  H01L21/336

CPC分类号： H01L29/1054 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834

摘要： A high capacity semiconductor device having a narrowed emitter layer. The semiconductor device includes a collector layer formed on a semiconductor substrate. An SiGe alloy layer is formed on the collector layer. A silicon film is formed on the SiGe layer. An emitter electrode is formed on the silicon film. A side wall film covers the side surface of the emitter electrode. The bottom surface of the emitter electrode is located above the lower surface of the side wall film. Part of the second region of the silicon film is located between the SiGe alloy layer and the side wall film. An impurity region is formed adjacent to the conductive layer. A silicide film is formed along the side surface of the second region, the side surface of the conductive layer, and the surface of the impurity region.

公开(公告)号：US20070111459A1

公开(公告)日：2007-05-17

申请号：US11594986

申请日：2006-11-09

申请人： Daichi Suma ,  Yoshikazu Ibara ,  Tatsuhiko Koide ,  Koichi Saito

发明人： Daichi Suma ,  Yoshikazu Ibara ,  Tatsuhiko Koide ,  Koichi Saito

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0817 ,  H01L29/7378

摘要： A semiconductor device manufacturing method including forming a conductive layer and a silicon film on a semiconductor substrate including an active region, forming an emitter electrode containing a first impurity on the silicon film above the active region, partially etching the silicon film using the emitter electrode as a mask, forming an insulative film covering the semiconductor substrate and a side wall film covering a side surface of the emitter electrode, introducing a second impurity into the conductive layer and silicon film so that the second impurity reaches the active region to form an impurity region containing the second impurity in parts of the conductive layer and silicon film, and diffusing the first impurity contained in the emitter electrode into the silicon film to form in the silicon film a first region containing the first impurity and a second region free of the first impurity.

摘要翻译： 一种半导体器件制造方法，包括在包括有源区的半导体衬底上形成导电层和硅膜，在有源区上方的硅膜上形成含有第一杂质的发射极，使用发射极部分地蚀刻硅膜作为 掩模，形成覆盖半导体衬底的绝缘膜和覆盖发射电极的侧表面的侧壁膜，将第二杂质引入到导电层和硅膜中，使得第二杂质到达有源区以形成杂质区 在导电层和硅膜的部分中含有第二杂质，并且将包含在发射电极中的第一杂质扩散到硅膜中，以在硅膜中形成含有第一杂质的第一区域和不含第一杂质的第二区域 。

公开(公告)号：US07723784B2

公开(公告)日：2010-05-25

申请号：US12399649

申请日：2009-03-06

申请人： Syouji Miyahara ,  Daichi Suma

发明人： Syouji Miyahara ,  Daichi Suma

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811

摘要： A well region in which an insulated gate semiconductor element is formed is a diffusion region, and an impurity concentration of the well region is lower toward its bottom portion. This leads to a problem of increased resistance. Therefore, particularly, an insulated gate semiconductor element having an up-drain structure has a problem of increased on-resistance. A p type well region is formed by stacking two p type impurity regions on one another. The p type impurity regions are allowed to serve as the p type well region by sequentially stacking n type semiconductor layers, on one another, having p type impurities implanted into their surfaces and simultaneously diffusing the impurities by heat treatment. In this way, it is possible to obtain the p type well region in which an impurity concentration sufficient to secure a desired breakdown voltage is maintained approximately uniform up to a desired depth.

摘要翻译： 其中形成绝缘栅极半导体元件的阱区是扩散区，并且阱区的杂质浓度朝向其底部较低。 这导致阻力增加的问题。 因此，特别地，具有上溢结构的绝缘栅半导体元件具有导通电阻增加的问题。 p型阱区通过彼此堆叠两个p型杂质区而形成。 通过依次堆叠n型半导体层，将p型杂质注入其表面并同时通过热处理扩散杂质，使p型杂质区域用作p型阱区。 以这种方式，可以获得其中足以确保所需击穿电压的杂质浓度保持大致均匀至所需深度的p型阱区。

公开(公告)号：US07446009B2

公开(公告)日：2008-11-04

申请号：US11594986

申请日：2006-11-09

申请人： Daichi Suma ,  Yoshikazu Ibara ,  Tatsuhiko Koide ,  Koichi Saito

发明人： Daichi Suma ,  Yoshikazu Ibara ,  Tatsuhiko Koide ,  Koichi Saito

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0817 ,  H01L29/7378

摘要： A semiconductor device manufacturing method including forming a conductive layer and a silicon film on a semiconductor substrate including an active region, forming an emitter electrode containing a first impurity on the silicon film above the active region, partially etching the silicon film using the emitter electrode as a mask, forming an insulative film covering the semiconductor substrate and a side wall film covering a side surface of the emitter electrode, introducing a second impurity into the conductive layer and silicon film so that the second impurity reaches the active region to form an impurity region containing the second impurity in parts of the conductive layer and silicon film, and diffusing the first impurity contained in the emitter electrode into the silicon film to form in the silicon film a first region containing the first impurity and a second region free of the first impurity.

摘要翻译： 一种半导体器件制造方法，包括在包括有源区的半导体衬底上形成导电层和硅膜，在有源区上方的硅膜上形成含有第一杂质的发射极，使用发射极部分地蚀刻硅膜作为 掩模，形成覆盖半导体衬底的绝缘膜和覆盖发射电极的侧表面的侧壁膜，将第二杂质引入到导电层和硅膜中，使得第二杂质到达有源区以形成杂质区 在导电层和硅膜的部分中含有第二杂质，并且将包含在发射电极中的第一杂质扩散到硅膜中，以在硅膜中形成含有第一杂质的第一区域和不含第一杂质的第二区域 。

公开(公告)号：US07129530B2

公开(公告)日：2006-10-31

申请号：US11237834

申请日：2005-09-29

申请人： Koichi Saito ,  Yoshikazu Ibara ,  Tatsuhiko Koide ,  Daichi Suma

发明人： Koichi Saito ,  Yoshikazu Ibara ,  Tatsuhiko Koide ,  Daichi Suma

IPC分类号： H01L29/739

CPC分类号： H01L29/1054 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834

摘要： A high capacity semiconductor device having a narrowed emitter layer. The semiconductor device includes a collector layer formed on a semiconductor substrate. An SiGe alloy layer is formed on the collector layer. A silicon film is formed on the SiGe layer. An emitter electrode is formed on the silicon film. A side wall film covers the side surface of the emitter electrode. The bottom surface of the emitter electrode is located above the lower surface of the side wall film. Part of the second region of the silicon film is located between the SiGe alloy layer and the side wall film. An impurity region is formed adjacent to the conductive layer. A silicide film is formed along the side surface of the second region, the side surface of the conductive layer, and the surface of the impurity region.

摘要翻译： 具有变窄的发射极层的大容量半导体器件。 半导体器件包括形成在半导体衬底上的集电极层。 在集电极层上形成SiGe合金层。 在SiGe层上形成硅膜。 在硅膜上形成发射电极。 侧壁膜覆盖发射电极的侧表面。 发射电极的底面位于侧壁膜的下表面之上。 硅膜的第二区域的一部分位于SiGe合金层和侧壁膜之间。 在导电层附近形成杂质区。 沿着第二区域的侧表面，导电层的侧表面和杂质区域的表面形成硅化物膜。

公开(公告)号：US20060065950A1

公开(公告)日：2006-03-30

申请号：US11239105

申请日：2005-09-30

申请人： Tatsuhiko Koide ,  Yoshikazu Ibara ,  Koichi Saito ,  Daichi Suma ,  Reiki Fujimori

发明人： Tatsuhiko Koide ,  Yoshikazu Ibara ,  Koichi Saito ,  Daichi Suma ,  Reiki Fujimori

IPC分类号： H01L29/00

CPC分类号： H01L29/66242

摘要： A high performance semiconductor device including a silicon oxide film that surrounds an SiGe alloy layer, which functions as a base layer, and an n-type diffusion layer, which functions as an emitter layer. Under a polycrystalline silicon film, the silicon oxide film extends over a boundary between an active region and an element isolation film. After a flat interlayer dielectric is formed, a lead wire is connected to a silicide film located above the isolation film.

摘要翻译： 包含作为发光层发挥作用的SiGe合金层作为基底层的氧化硅膜和n型扩散层的高性能半导体装置。 在多晶硅膜下面，氧化硅膜在有源区和元件隔离膜之间的边界上延伸。 在形成平坦的层间电介质之后，引线与位于隔离膜上方的硅化物膜连接。