公开(公告)号：US06360285B1

公开(公告)日：2002-03-19

申请号：US08269234

申请日：1994-06-30

申请人： David M. Fenwick ,  Denis Foley ,  David Hartwell ,  Ricky C. Hetherington ,  Dale R. Keck ,  Elbert Bloom

发明人： David M. Fenwick ,  Denis Foley ,  David Hartwell ,  Ricky C. Hetherington ,  Dale R. Keck ,  Elbert Bloom

IPC分类号： G06F1202

CPC分类号： G06F13/16

摘要： In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank busy signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus and include logic, responsive to the memory bank available signals for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus. This avoids stalling the system bus and improves system performance by allowing all initiated transactions to complete as quickly as possible.

摘要翻译： 根据本发明，一种装置包括具有存储体可用信号的系统总线。 耦合到系统总线的是至少两个存储器模块，每个存储器模块具有至少一个存储体。 每个存储器模块包括用于将每个存储体与存储器组可用信号之一相关联的机构。 此外，每个存储器模块包括用于确定每个存储体的可用性状态的逻辑，并且用于向相关联的存储器组忙信号提供反映存储体的可用性状态的值。 此外，至少两个指令器模块耦合到系统总线，并且包括逻辑，响应于存储器组可用信号，以防止当指挥官试图访问被确定为不可用的存储体时指挥官模块获得对系统总线的控制 。 通过这样的布置，只有寻求访问可用存储体的指挥官模块将被允许获得对系统总线的控制。 这样可以避免系统总线停滞，并通过允许所有启动的事务尽快完成来提高系统性能。

公开(公告)号：US4449182A

公开(公告)日：1984-05-15

申请号：US308826

申请日：1981-10-05

申请人： Barry L. Rubinson ,  Edward A. Gardner ,  William A. Grace ,  Richard F. Lary ,  Dale R. Keck

发明人： Barry L. Rubinson ,  Edward A. Gardner ,  William A. Grace ,  Richard F. Lary ,  Dale R. Keck

IPC分类号： G06F15/16 ,  G06F5/06 ,  G06F9/445 ,  G06F9/52 ,  G06F12/00 ,  G06F13/12 ,  G06F13/20 ,  G06F13/38 ,  G06F15/167 ,  G06F15/173 ,  G06F15/177 ,  H04L13/08 ,  G06F9/46

CPC分类号： G06F9/4405 ,  G06F13/126 ,  G06F15/17356 ,  G06F15/177

摘要： An interface mechanism (10) between two processors, such as a host processor (70) and a processor (31) in an intelligent controller (30) for mass storage devices (40), and utilizing a set of data structures employing a dedicated communications region (80A) in host memory (80). Interprocessor commands and responses are communicated as packets over an I/O bus (60) of the host (70), to and from the communication region (80A), through a pair of ring-type queues (80D) and (80E). The entry of each ring location (e.g., 132, 134, 136, 138) points to another location in the communications region where a command or response is placed. The filling and emptying of ring entries (132-138) is controlled through the use of an `ownership` byte or bit (278) associated with each entry. The ownership bit (278) is placed in a first state when the message source (70 or 31) has filled the entry and in a second state when the entry has been emptied. Each processor keeps track of the rings' status, to prevent the sending of more messages than the rings can hold. These rings permit each processor to operate at its own speed, without creating race conditions and obviate the need for hardware interlock capability on the I/O bus (60).

摘要翻译： 在用于大容量存储设备（40）的智能控制器（30）中的诸如主机处理器（70）和处理器（31）的两个处理器之间的接口机构（10），并且利用采用专用通信的一组数据结构 主机存储器（80）中的区域（80A）。 处理器的命令和响应通过主机（70）的I / O总线（60）通过一对环型队列（80D）和（80E）传送到通信区域（80A）和/或从通信区域（80A）传送。 每个环位置的输入（例如，132,134,136,138）指向放置命令或响应的通信区域中的另一位置。 通过使用与每个条目相关联的“所有权”字节或位（278）来控制环形条目（132-138）的填充和排空。 当消息源（70或31）已经填充条目时，所有权位（278）被置于第一状态，并且当条目被清空时处于第二状态。 每个处理器跟踪环的状态，以防止发送比环可以容纳更多的消息。 这些环允许每个处理器以自己的速度运行，而不会产生竞争条件，从而避免了I / O总线（60）上硬件互锁能力的需要。

公开(公告)号：US5737546A

公开(公告)日：1998-04-07

申请号：US775552

申请日：1996-12-31

申请人： David M. Fenwick ,  Denis J. Foley ,  Stephen R. Van Doren ,  Dale R. Keck

发明人： David M. Fenwick ,  Denis J. Foley ,  Stephen R. Van Doren ,  Dale R. Keck

IPC分类号： G06F13/42 ,  G06F13/00 ,  G06F13/368

CPC分类号： G06F13/4213

摘要： Bus interfaces for nodes coupled to a system bus in a computer system, the system bus including an address bus and a separate data bus. System bus operations include address and command transactions and data transactions. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. A bus interface may include any of a commander address bus interface means for providing to an address bus address and command transactions, a responder address bus interface means for acknowledging receipt of address and command transactions via the address bus, a commander data bus interface means for controlling submission to the data bus of data transactions as a result of the occurrence of address and command transactions on the address bus, and a responder data bus interface means for transferring data on the data bus during a data transaction. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. In particular, the timing of data transactions and the rate at which data transactions occur on the data bus is independent of the timing of address and command transactions and the rate at which address sub-transactions occur on the address bus.

摘要翻译： 耦合到计算机系统中的系统总线的节点的总线接口，系统总线包括地址总线和单独的数据总线。 系统总线操作包括地址和命令事务和数据事务。 在数据总线上分别发生数据事务，与地址总线上地址和命令事务的发生无关。 总线接口可以包括用于向地址总线地址和命令事务提供的指挥官地址总线接口装置中的任一个，用于通过地址总线确认接收地址和命令事务的响应方地址总线接口装置，用于 由于在地址总线上发生地址和命令事务而导致数据事务的数据总线的提交;以及响应者数据总线接口装置，用于在数据事务期间在数据总线上传送数据。 在数据总线上分别发生数据事务，与地址总线上地址和命令事务的发生无关。 特别地，数据事务的定时和数据事务在数据总线上发生的速率与地址和命令事务的定时以及地址总线上发生地址子事务的速率无关。