公开(公告)号：US06360285B1

公开(公告)日：2002-03-19

申请号：US08269234

申请日：1994-06-30

申请人： David M. Fenwick ,  Denis Foley ,  David Hartwell ,  Ricky C. Hetherington ,  Dale R. Keck ,  Elbert Bloom

发明人： David M. Fenwick ,  Denis Foley ,  David Hartwell ,  Ricky C. Hetherington ,  Dale R. Keck ,  Elbert Bloom

IPC分类号： G06F1202

CPC分类号： G06F13/16

摘要： In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank busy signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus and include logic, responsive to the memory bank available signals for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus. This avoids stalling the system bus and improves system performance by allowing all initiated transactions to complete as quickly as possible.

摘要翻译： 根据本发明，一种装置包括具有存储体可用信号的系统总线。 耦合到系统总线的是至少两个存储器模块，每个存储器模块具有至少一个存储体。 每个存储器模块包括用于将每个存储体与存储器组可用信号之一相关联的机构。 此外，每个存储器模块包括用于确定每个存储体的可用性状态的逻辑，并且用于向相关联的存储器组忙信号提供反映存储体的可用性状态的值。 此外，至少两个指令器模块耦合到系统总线，并且包括逻辑，响应于存储器组可用信号，以防止当指挥官试图访问被确定为不可用的存储体时指挥官模块获得对系统总线的控制 。 通过这样的布置，只有寻求访问可用存储体的指挥官模块将被允许获得对系统总线的控制。 这样可以避免系统总线停滞，并通过允许所有启动的事务尽快完成来提高系统性能。

公开(公告)号：US4864496A

公开(公告)日：1989-09-05

申请号：US93488

申请日：1987-09-04

申请人： Victoria M. Triolo ,  Elbert Bloom ,  David W. Hartwell

发明人： Victoria M. Triolo ,  Elbert Bloom ,  David W. Hartwell

IPC分类号： G06F13/40

CPC分类号： G06F13/405

摘要： A control adapter module in a bus adapter connecting a high-speed pended bus to a slower speed non-pended bus functions as a node of the non-pended bus. An interconnect bus extends between the control module and a response adapter module functioning as a node on the pended bus. Control signals on the interconnect bus generated by the response module comprise status signals having an indefinite assertion duration, and are deasserted only in response to control signals on the interconnect bus generated by the control module, which have a finite duration. Control signals on the interconnect bus generated by the response module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the clock signal of the non-pended bus. Control signals on the interconnect bus generated by the control module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the pended bus clock signal.

摘要翻译： 总线适配器中的控制适配器模块将高速挂起总线连接到较慢速度的非挂起总线，作为非挂起总线的节点。 互连总线在控制模块和作为挂起总线上的节点的响应适配器模块之间延伸。 由响应模块产生的互连总线上的控制信号包括具有不确定的断言持续时间的状态信号，并且仅响应于由具有有限持续时间的控制模块产生的互连总线上的控制信号而被解除置位。 由响应模块生成的互连总线上的控制信号由双级同步器同步，该双级同步器由从非等效总线的时钟信号导出的多相时钟信号的两相控制。 由控制模块生成的互连总线上的控制信号由双级同步器同步，该双级同步器由从有争议的总线时钟信号导出的多相时钟信号的两相控制。

公开(公告)号：US5666551A

公开(公告)日：1997-09-09

申请号：US590802

申请日：1996-01-24

申请人： David M. Fenwick ,  Denis J. Foley ,  Stephen R. Van Doren ,  David W. Hartwell ,  Elbert Bloom ,  Ricky C. Hetherington

发明人： David M. Fenwick ,  Denis J. Foley ,  Stephen R. Van Doren ,  David W. Hartwell ,  Elbert Bloom ,  Ricky C. Hetherington

IPC分类号： G06F11/00 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F11/076 ,  G06F13/4217

摘要： A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. A mechanism for tracking address and command transactions occurring on the bus produces, for each address and command transaction occurring on the address bus, a corresponding sequence number tag. Those sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node are stored by the data bus sequencer. The data bus sequencer further includes circuitry for counting the number of data transactions occurring on the data bus, comparing the counted number of data transactions to the stored sequence number tags and initiating data transactions on the data bus in response to the comparison.

摘要翻译： 数据总线排序器，用于耦合到系统总线的节点，用于将数据事务和总线上的地址事务相关联。 用于跟踪在总线上发生的地址和命令事务的机制针对地址总线上发生的每个地址和命令事务产生相应的序列号标签。 由数据总线排序器存储与节点发起数据事务的地址和命令事务对应的那些序列号标签。 数据总线序列器还包括用于对在数据总线上发生的数据事务的数量进行计数的电路，将计数的数据事务数与存储的序列号标签进行比较，并响应于该比较在数据总线上启动数据事务。

公开(公告)号：US6076129A

公开(公告)日：2000-06-13

申请号：US869610

申请日：1997-06-06

申请人： David M. Fenwick ,  Denis J. Foley ,  Stephen R. Van Doren ,  David W. Hartwell ,  Elbert Bloom ,  Ricky C. Hetherington

发明人： David M. Fenwick ,  Denis J. Foley ,  Stephen R. Van Doren ,  David W. Hartwell ,  Elbert Bloom ,  Ricky C. Hetherington

IPC分类号： G06F11/00 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F11/076 ,  G06F13/4217

摘要： A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. The data bus sequencer includes means for tracking address and command transactions occurring on an address bus, the means for tracking producing a sequence number tag corresponding to each address and command transaction occurring on the address bus. Means for associating data transactions with address and command transactions stores the sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node. Further included are means for tracking data transactions occurring on a data bus, means for comparing tracked data transactions to associated data transactions, and means for initiating data transactions on the data bus in response to the comparison. The data bus sequencer further includes means for driving the sequence tag for an address and command transaction to which a data transaction is associated on the data bus. Consistency check means includes means for tracking data transactions occurring on a data bus, and means for comparing tracked data transactions to sequence number tags driven on the data bus. The consistency check means indicates an error condition in response to the comparison if the sequence number tag most recently driven on the data bus is not equal to the counted number of data transactions which have occurred on the data bus.

摘要翻译： 数据总线排序器，用于耦合到系统总线的节点，用于将数据事务和总线上的地址事务相关联。 数据总线定序器包括用于跟踪在地址总线上发生的地址和命令事务的装置，用于跟踪的装置产生对应于地址总线上发生的每个地址和命令事务的序列号标签。 用于将数据事务与地址和命令事务相关联的手段存储对应于由节点发起数据事务的地址和命令事务的序列号标签。 还包括用于跟踪在数据总线上发生的数据交易的装置，用于将跟踪的数据交易与相关联的数据交易进行比较的装置，以及用于响应于比较在数据总线上启动数据交易的装置。 数据总线序列器还包括用于驱动序列标签的装置，用于在数据总线上与数据事务相关联的地址和命令事务。 一致性检查装置包括用于跟踪在数据总线上发生的数据交易的装置，以及用于将跟踪的数据事务与在数据总线上驱动的序列号标签进行比较的装置。 如果最近在数据总线上驱动的序列号标签不等于在数据总线上发生的数据交易的计数，则一致性检查装置响应于比较来指示错误状况。

公开(公告)号：US4858234A

公开(公告)日：1989-08-15

申请号：US93476

申请日：1987-09-04

申请人： David W. Hartwell ,  Elbert Bloom ,  Victoria M. Triolo

发明人： David W. Hartwell ,  Elbert Bloom ,  Victoria M. Triolo

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F11/14

CPC分类号： G06F11/0745 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/14

摘要： A bus adapter interconnecting a system bus and an I/O bus over an interconnect bus generates a first READ signal by decoding the command lines of the I/O bus and supplying the READ command signal across the interconnect bus. The command lines are also provided across the interconnect bus and are decoded on the system bus side of the interconnect bus to form a second READ signal. The first and second READ signals and a parity error signal are processed on the system bus side of the interconnect bus to generate a NON-RECOVERABLE ERROR signal to initiate a system shut-down when a parity error occurs during a disconnected WRITE transaction and to generate a RECOVERABLE ERROR signal to initiate a repeat of the transaction when a parity error occurs during a READ transaction.

摘要翻译： 通过互连总线互连系统总线和I / O总线的总线适配器通过对I / O总线的命令行进行解码并通过互连总线提供READ命令信号来产生第一READ信号。 命令行也跨越互连总线提供，并且在互连总线的系统总线侧进行解码以形成第二READ信号。 在互连总线的系统总线侧处理第一和第二READ信号和奇偶校验错误信号，以产生非可恢复错误信号，以在断开的写入事务期间发生奇偶校验错误时发起系统关闭并产生 当在READ事务期间发生奇偶校验错误时，RECOVERABLE ERROR信号用于启动事务的重复。

公开(公告)号：US4837767A

公开(公告)日：1989-06-06

申请号：US93480

申请日：1987-09-04

申请人： David W. Hartwell ,  Elbert Bloom ,  Victoria M. Triolo

发明人： David W. Hartwell ,  Elbert Bloom ,  Victoria M. Triolo

IPC分类号： G06F11/10 ,  G06F11/14

CPC分类号： G06F11/141 ,  G06F11/10

摘要： A bus adapter interconnecting a system bus and an I/O bus over an interconnect bus generates a first READ signal by decoding the command lines of the I/O bus and supplying the READ command signal across the interconnect bus. The command lines are also provided across the interconnect bus and are decoded on the system bus side of the interconnect bus to form a second READ signal. The first and second READ signals and a parity error signal are processed on the system bus side of the interconnect bus to generate a NON-RECOVERABLE ERROR signal to initiate a system shut-down when a parity error occurs during a disconnected WRITE transaction and to generate a RECOVERABLE ERROR signal to initiate a repeat of the transaction when a parity error occurs during a READ transaction.

摘要翻译： 通过互连总线互连系统总线和I / O总线的总线适配器通过对I / O总线的命令行进行解码并通过互连总线提供READ命令信号来产生第一READ信号。 命令行也跨越互连总线提供，并且在互连总线的系统总线侧进行解码以形成第二READ信号。 在互连总线的系统总线侧处理第一和第二READ信号和奇偶校验错误信号，以产生非可恢复错误信号，以在断开的写入事务期间发生奇偶校验错误时发起系统关闭并产生 当在READ事务期间发生奇偶校验错误时，RECOVERABLE ERROR信号用于启动事务的重复。

公开(公告)号：US4979097A

公开(公告)日：1990-12-18

申请号：US93479

申请日：1987-09-04

申请人： Victoria M. Triolo ,  Elbert Bloom ,  David W. Hartwell

发明人： Victoria M. Triolo ,  Elbert Bloom ,  David W. Hartwell

IPC分类号： G06F13/36 ,  G06F5/06 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F5/06 ,  G06F13/405 ,  G06F13/4226

摘要： A bus adapter connecting a high-speed pended bus to a slower speed non-pended bus includes a first module functioning as a node of the pended bus and a second module functioning as a node of the non-pended bus. An interconnect bus extends between the two modules. Control signals on the interconnect bus generated by the first module comprise status signals having an indefinite assertion duration, and are deasserted only in response to control signals on the interconnect bus generated by the second module, which have a finite duration. Control signals on the interconnect bus generated by the first module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the clock signal of the non-pended bus. Control signals on the interconnect bus generated by the second module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the pended bus clock signal.

摘要翻译： 将高速挂起总线连接到较慢速度的非挂起总线的总线适配器包括用作挂起总线的节点的第一模块和用作非挂起总线的节点的第二模块。 互连总线在两个模块之间延伸。 由第一模块产生的互连总线上的控制信号包括具有不确定断言持续时间的状态信号，并且仅响应于由具有有限持续时间的第二模块产生的互连总线上的控制信号而被解除置位。 由第一模块产生的互连总线上的控制信号由由等级不等式总线的时钟信号导出的多相时钟信号的两相控制的双等级同步器同步。 由第二模块产生的互连总线上的控制信号由双级同步器同步，双等级同步器由从有争议的总线时钟信号导出的多相时钟信号的两相控制。