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1.发明授权Extended main memory hierarchy having flash memory for page fault handling 有权具有用于页面故障处理的闪存的扩展主存储器层次结构公开(公告)号：US09208084B2
公开(公告)日：2015-12-08
申请号：US12493779
申请日：2009-06-29
CPC分类号： G06F12/08 , G06F12/10 , G06F2212/202 , G06F2212/2022 , G06F2212/205 , Y02D10/13
摘要： A computer system with flash memory in the main memory hierarchy is disclosed. In an embodiment, the computer system includes at least one processor, a memory management unit coupled to the at least one processor, and a random access memory (RAM) coupled to the memory management unit. The computer system may also include a flash memory coupled to the memory management unit, wherein the computer system is configured to store at least a subset of a plurality of pages in the flash memory during operation. Responsive to a page fault, the memory management unit may determine, without invoking an I/O driver, if a requested page associated with the page fault is stored in the flash memory and further configured to, if the page is stored in the flash memory, transfer the page into RAM.
摘要翻译： 公开了具有主存储器层级中的闪存的计算机系统。 在一个实施例中，计算机系统包括耦合到至少一个处理器的至少一个处理器，存储器管理单元和耦合到存储器管理单元的随机存取存储器（RAM）。 计算机系统还可以包括耦合到存储器管理单元的闪存，其中计算机系统被配置为在操作期间将多个页面的至少一个子集存储在闪存中。 响应于页面故障，存储器管理单元可以在不调用I / O驱动器的情况下确定与页面错误相关联的请求的页面是否存储在闪存中，并且还被配置为，如果页面存储在闪存中 ，将页面传输到RAM中。
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2.发明申请公开(公告)号：US20100332727A1
公开(公告)日：2010-12-30
申请号：US12493779
申请日：2009-06-29
CPC分类号： G06F12/08 , G06F12/10 , G06F2212/202 , G06F2212/2022 , G06F2212/205 , Y02D10/13
摘要： A computer system with flash memory in the main memory hierarchy is disclosed. In an embodiment, the computer system includes at least one processor, a memory management unit coupled to the at least one processor, and a random access memory (RAM) coupled to the memory management unit. The computer system may also include a flash memory coupled to the memory management unit, wherein the computer system is configured to store at least a subset of a plurality of pages in the flash memory during operation. Responsive to a page fault, the memory management unit may determine, without invoking an I/O driver, if a requested page associated with the page fault is stored in the flash memory and further configured to, if the page is stored in the flash memory, transfer the page into RAM.
摘要翻译： 公开了具有主存储器层级中的闪存的计算机系统。 在一个实施例中，计算机系统包括耦合到至少一个处理器的至少一个处理器，存储器管理单元和耦合到存储器管理单元的随机存取存储器（RAM）。 计算机系统还可以包括耦合到存储器管理单元的闪存，其中计算机系统被配置为在操作期间将多个页面的至少一个子集存储在闪存中。 响应于页面故障，存储器管理单元可以在不调用I / O驱动器的情况下确定与页面错误相关联的请求的页面是否存储在闪存中，并且还被配置为，如果页面存储在闪存中 ，将页面传输到RAM中。
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公开(公告)号：US20100293420A1
公开(公告)日：2010-11-18
申请号：US12466643
申请日：2009-05-15
CPC分类号： G06F12/08 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/123 , G06F2212/1024 , G06F2212/205 , G06F2212/683 , G06F2212/7203
摘要： System and method for using flash memory in a memory hierarchy. A computer system includes a processor coupled to a memory hierarchy via a memory controller. The memory hierarchy includes a cache memory, a first memory region of random access memory coupled to the memory controller via a first buffer, and an auxiliary memory region of flash memory coupled to the memory controller via a flash controller. The first buffer and the flash controller are coupled to the memory controller via a single interface. The memory controller receives a request to access a particular page in the first memory region. The processor detects a page fault corresponding to the request and in response, invalidates cache lines in the cache memory that correspond to the particular page, flushes the invalid cache lines, and swaps a page from the auxiliary memory region to the first memory region.
摘要翻译： 在内存层次结构中使用闪存的系统和方法。 计算机系统包括经由存储器控制器耦合到存储器层级的处理器。 存储器层级包括高速缓冲存储器，经由第一缓冲器耦合到存储器控制器的随机存取存储器的第一存储器区域以及经由闪存控制器耦合到存储器控制器的闪存的辅助存储器区域。 第一缓冲器和闪存控制器通过单个接口耦合到存储器控制器。 存储器控制器接收访问第一存储器区域中的特定页面的请求。 处理器检测与该请求相对应的页面错误，并且作为响应，使对应于特定页面的高速缓冲存储器中的高速缓存行无效，刷新无效高速缓存行，并将页面从辅助存储器区域交换到第一存储器区域。
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公开(公告)号：US07529894B2
公开(公告)日：2009-05-05
申请号：US11205706
申请日：2005-08-17
IPC分类号： G06F12/00
CPC分类号： G06F13/28 , G06F12/0813 , G06F12/0815 , G06F12/0831
摘要： In one embodiment, a node comprises at least one memory control unit configured to couple to an industry standard memory interface for coupling to a memory; and at least one coherence unit configured to transmit and receive coherence messages to and from other nodes to maintain coherent memory among the nodes. The coherence messages are conveyed on a second interface to which the coherence unit is coupled, wherein the second interface includes at least a physical layer as specified by the industry standard memory interface.
摘要翻译： 在一个实施例中，节点包括至少一个存储器控制单元，其被配置为耦合到工业标准存储器接口以耦合到存储器; 以及至少一个相干单元，被配置为向和从其他节点发送和接收相干消息以在所述节点之间维持相干存储器。 相干消息在相干单元耦合到的第二接口上传送，其中第二接口至少包括由工业标准存储器接口指定的物理层。
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5.发明授权Apparatus and method for fine-grained multithreading in a multipipelined processor core 有权多重处理器核心中的细粒度多线程的装置和方法公开(公告)号：US07401206B2
公开(公告)日：2008-07-15
申请号：US10880488
申请日：2004-06-30
IPC分类号： G06F9/34
CPC分类号： G06F9/3851 , G06F9/3885 , G06F12/0842 , G06F12/0859
摘要： An apparatus and method for fine-grained multithreading in a multipipelined processor core. According to one embodiment, a processor may include instruction fetch logic configured to assign a given one of a plurality of threads to a corresponding one of a plurality of thread groups, where each of the plurality of thread groups may comprise a subset of the plurality of threads, to issue a first instruction from one of the plurality of threads during one execution cycle, and to issue a second instruction from another one of the plurality of threads during a successive execution cycle. The processor may further include a plurality of execution units, each configured to execute instructions issued from a respective thread group.
摘要翻译： 一种用于多行处理器核心中的细粒度多线程的装置和方法。 根据一个实施例，处理器可以包括指令提取逻辑，其被配置为将多个线程中的给定一个线程分配给多个线程组中的相应一个线程组，其中多个线程组中的每一个可以包括多个线程组的子集 线程，以在一个执行周期期间从多个线程之一发出第一指令，并且在连续执行周期期间从多个线程中的另一个发出第二指令。 处理器还可以包括多个执行单元，每个执行单元被配置为执行从相应的线程组发出的指令。
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6.发明授权Apparatus and method for operating clock sensitive devices in multiple timing domains 失效用于在多个定时域中操作时钟敏感设备的装置和方法公开(公告)号：US06327667B1
公开(公告)日：2001-12-04
申请号：US08893309
申请日：1997-07-15
IPC分类号： G06F104
CPC分类号： G11C7/1072 , G06F12/0844
摘要： In a digital signal processing system, such as a computer system, an apparatus for communicating digital signals in a plurality of operating domains. The first domain has first timing and control signals synchronized to a first clock. In response to an event, the apparatus dynamically transitions the operation of the synchronous memory to a second domain having second timing and control signals synchronized to a second clock. The first timing and control signals being different in frequency, shape, and protocol than the second timing and control signals. The first clock can be a processor clock to synchronize communication of address and data signals with a processor, and the second clock can be a system clock to synchronize communication of address and data signals with an asynchronous data processing device such as random access memory.
摘要翻译： 在诸如计算机系统的数字信号处理系统中，用于在多个操作域中传送数字信号的装置。 第一域具有与第一时钟同步的第一定时和控制信号。 响应于事件，设备动态地将同步存储器的操作转换到具有与第二时钟同步的第二定时和控制信号的第二域。 第一定时和控制信号的频率，形状和协议与第二定时和控制信号不同。 第一时钟可以是处理器时钟，用于同步处理器的地址和数据信号的通信，并且第二时钟可以是用于将地址和数据信号的通信与异步数据处理设备（诸如随机存取存储器）进行同步的系统时钟。
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7.发明授权
公开(公告)号：US06154812A
公开(公告)日：2000-11-28
申请号：US881725
申请日：1997-06-25
IPC分类号： G06F12/08
CPC分类号： G06F12/0897
摘要： A data cache unit associated with a processor, the data cache unit including a first non-blocking cache receiving a data access from a device in the processor. A second non-blocking cache is coupled to the first non-blocking cache to service misses in the first non-blocking cache. A data return path coupled to the second non-blocking cache couples data returning from the second non-blocking cache to both the first non-blocking cache and the device generating the access to the first non-blocking cache.
摘要翻译： 与处理器相关联的数据高速缓存单元，所述数据高速缓存单元包括从所述处理器中的设备接收数据访问的第一非阻塞缓存。 第二非阻塞高速缓存耦合到第一非阻塞高速缓存以服务第一非阻塞高速缓存中的未命中。 耦合到第二非阻塞缓存的数据返回路径将从第二非阻塞高速缓存返回的数据与第一非阻塞高速缓存和产生对第一非阻塞高速缓存的访问的设备耦合。
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8.发明授权Method for thermal overload detection and prevention for an intergrated circuit processor 失效热过载保护方法，当超过热阈值时，产生不可屏蔽的中断，以降低集成电路的时钟频率
公开(公告)号：US5978864A
公开(公告)日：1999-11-02
申请号：US882610
申请日：1997-06-25
CPC分类号： G06F9/3891 , G06F1/206 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3857 , G06F9/3869 , G06F9/3885 , Y02B60/1275
摘要： A system and method for thermal overload detection and protection for a processor which allows the processor to run at near maximum potential for the vast majority of its execution life. This is effectuated by the provision of circuitry to detect when the processor has exceeded its thermal thresholds and which then causes the processor to automatically reduce the clock rate to a fraction of the nominal clock while execution continues. When the thermal condition has stabilized, the clock may be raised in a stepwise fashion back to the nominal clock rate. Throughout the period of cycling the clock frequency from nominal to minimum and back, the program continues to be executed. Also provided is a queue activity rise time detector and method to control the rate of acceleration of a functional unit from idle to full throttle by a localized stall mechanism at the boundary of each stage in the pipe. This mechanism can detect when an idle queue is suddenly overwhelmed with input such that over a short period of approximately 10-20 machine cycles, the queue activity rate has increased from idle to near stall threshold.
摘要翻译： 一种用于处理器的热过载检测和保护的系统和方法，其允许处理器在其绝大多数执行寿命期间以接近最大潜力运行。 这通过提供电路来检测何时处理器已经超过其热阈值并且然后使处理器在执行继续时自动将时钟速率降低到标称时钟的一小部分来实现。 当热条件稳定时，时钟可以逐步升高回到标称时钟速率。 在将时钟频率从标称到最小和反向的整个周期期间，程序继续执行。 还提供了一种队列活动上升时间检测器和方法，用于通过在管道中的每个阶段的边界处的局部失速机构来控制功能单元从怠速到全节气门的加速率。 这种机制可以检测空闲队列何时突然被输入压倒，使得在大约10-20个机器周期的短时间内，队列活动速率已经从空闲增加到接近失速阈值。
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9.发明授权Method for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cache 失效在多端口非阻塞缓存中执行串行库冲突检测和解析的方法
公开(公告)号：US5930819A
公开(公告)日：1999-07-27
申请号：US881238
申请日：1997-06-25
CPC分类号： G06F12/0851 , G06F12/0857
摘要： A data cache unit associated with a processor, the data cache unit including a multi-ported non-blocking cache receiving a data access request from a lower level device in the processor. A memory scheduling window includes at least one row of entries, wherein each entry includes an address field holding an address of the access request. A conflict map field within at least some of the entries is coupled to a conflict checking unit. The conflict checking unit responds to the address fields by setting bits in the conflict map fields to indicate intra-row conflicts between entries. A picker coupled to the memory scheduling window responds to the conflict map fields so as to identify groups of non-conflicting entries to launch in parallel at the multi-ported non-blocking cache.
摘要翻译： 与处理器相关联的数据高速缓存单元，所述数据高速缓存单元包括从所述处理器中的较低级别的设备接收数据访问请求的多端口非阻塞高速缓存。 存储器调度窗口包括至少一行条目，其中每个条目包括保存访问请求的地址的地址字段。 至少一些条目内的冲突映射字段被耦合到冲突检查单元。 冲突检查单元通过设置冲突映射字段中的位来指示地址字段来指示条目之间的行内冲突。 耦合到存储器调度窗口的选择器响应于冲突映射字段，以便识别在多端口非阻塞高速缓存上并行启动的非冲突条目的组。
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10.发明授权Reducing cache misses by snarfing writebacks in non-inclusive memory systems 失效通过在非包容性内存系统中缩写回写来减少高速缓存未命中
公开(公告)号：US5909697A
公开(公告)日：1999-06-01
申请号：US940219
申请日：1997-09-30
申请人： Norman M. Hayes , Ricky C. Hetherington , Belliappa M. Kuttanna , Fong Pong , Krishna M. Thatipelli
发明人： Norman M. Hayes , Ricky C. Hetherington , Belliappa M. Kuttanna , Fong Pong , Krishna M. Thatipelli
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A non-inclusive multi-level cache memory system is optimized by removing a first cache content from a first cache, so as to provide cache space in the first cache. In response to a cache miss in the first and second caches, the removed first cache content is stored in a second cache. All cache contents that are stored in the second cache are limited to have read-only attributes so that if any copies of the cache contents in the second cache exist in the cache memory system, a processor or equivalent device must seek permission to access the location in which that copy exists, ensuring cache coherency. If the first cache content is required by a processor (e.g., when a cache hit occurs in the second cache for the first cache content), room is again made available, if required, in the first cache by selecting a second cache content from the first cache and moving it to the second cache. The first cache content is then moved from the second cache to the first cache, rendering the first cache available for write access. Limiting the second cache to read-only access reduces the number of status bits per tag that are required to maintain cache coherency. In a cache memory system using a MOESI protocol, the number of status bits per tag is reduced to a single bit for the second cache, reducing tag overhead and minimizing silicon real estate used when placed on-chip to improve cache bandwidth.
摘要翻译： 通过从第一高速缓存中移除第一高速缓存内容来优化非包容性多级缓存存储器系统，以便在第一高速缓存中提供高速缓存空间。 响应于第一和第二高速缓存中的高速缓存未命中，将移除的第一高速缓存内容存储在第二高速缓存中。 存储在第二高速缓存中的所有高速缓存内容被限制为具有只读属性，使得如果高速缓冲存储器系统中存在第二缓存中的高速缓存内容的任何副本，则处理器或等效设备必须寻求访问该位置的许可 其中存在该副本，确保高速缓存一致性。 如果处理器需要第一高速缓存内容（例如，当高速缓存命中发生在第一高速缓存内容的第二高速缓存中时），则如果需要，再次通过从第一高速缓存中选择第二高速缓存内容来在第一高速缓存中提供空间 第一个缓存并将其移动到第二个缓存。 然后将第一高速缓存内容从第二高速缓存移动到第一高速缓存，使得第一高速缓存可用于写访问。 将第二个缓存限制为只读访问减少了维护高速缓存一致性所需的每个标记的状态位数。 在使用MOESI协议的高速缓冲存储器系统中，每个标签的状态位的数量减少到第二高速缓存的单个位，减少标签开销并最小化放置在片上时使用的硅空间以提高高速缓存带宽。
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