公开(公告)号：US06268293B1

公开(公告)日：2001-07-31

申请号：US09442956

申请日：1999-11-18

申请人： Lawrence Clevenger ,  Greg Costrini ,  Dave Dobuzinsky ,  Yoichi Otani ,  Thomas Rupp ,  Viraj Sardesai

发明人： Lawrence Clevenger ,  Greg Costrini ,  Dave Dobuzinsky ,  Yoichi Otani ,  Thomas Rupp ,  Viraj Sardesai

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/76802

摘要： A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000 watts under a pressure of 50-400 mTorr. The gas mixture includes 2-30 sccm of C4F8, 20-80 sccm of CO, 2-30 sccm of O2 and 50-400 sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.

摘要翻译： 在集成电路芯片中形成导线的镶嵌方法。 通过在50-400mTorr的压力下以500至3000瓦的电容耦合气体混合物形成的等离子体蚀刻沟槽。 气体混合物包括2-30sccm的C 4 F 8，20-80sccm的CO，2-30sccm的O 2和50-400sccm的Ar。 可以将气体流量调节到最佳水平，从而实现高度的均匀性。 低于所选均匀度的晶片可能会重新加工。 在具有可接受流动的沟槽中形成的镶嵌布线层表现出高度的薄层电阻均匀性和改善的线对线短路产量。