公开(公告)号：US06865644B2

公开(公告)日：2005-03-08

申请号：US09915024

申请日：2001-07-25

申请人： Raymond R. Husted ,  Ronald E. Schultz ,  Dennis J. Dombrosky ,  David A. Karpuszka

发明人： Raymond R. Husted ,  Ronald E. Schultz ,  Dennis J. Dombrosky ,  David A. Karpuszka

IPC分类号： G05B19/05 ,  G06F13/10

CPC分类号： G05B19/054

摘要： A system and method for industrial control I/O forcing is provided. The invention includes a processor, shared memory and an I/O processor with cache memory. The invention provides for the cache memory to be loaded with I/O force data from the shared memory. The I/O processor performs I/O forcing utilizing the I/O force data stored in the cache memory. The invention further provides for the processor to notify the I/O processor in the event that I/O force data is altered during control program execution. The invention further provides for the I/O processor to refresh the cache memory (e.g., via a blocked write) after receipt of alteration of the I/O force data from the processor.

摘要翻译： 提供了工业控制I / O强制的系统和方法。 本发明包括处理器，共享存储器和具有高速缓冲存储器的I / O处理器。 本发明提供了从共享存储器加载I / O力数据的高速缓冲存储器。 I / O处理器使用存储在高速缓冲存储器中的I / O力数据来执行I / O强制。 本发明还提供了在控制程序执行期间I / O力数据被改变的情况下，处理器通知I / O处理器。 本发明进一步提供I / O处理器在接收到来自处理器的I / O力数据的改变之后刷新高速缓冲存储器（例如经由阻塞的写入）。

公开(公告)号：US08364291B2

公开(公告)日：2013-01-29

申请号：US12242223

申请日：2008-09-30

申请人： William B. Cook ,  David A. Karpuszka

发明人： William B. Cook ,  David A. Karpuszka

IPC分类号： G05B9/03 ,  G05B15/02

CPC分类号： G05B9/03 ,  G05B19/058 ,  G05B2219/14131 ,  G05B2219/15079

摘要： An industrial control system implementing a multi-tasking operating system employs a primary and secondary controller each having a processor and an I/O data table. The processors are configured to execute one or more priority ranked programs. A tracking of changes in the I/O data table of the primary processor is used to independently track changes to controller specific data that has been changed and program specific data that has been changed and to transmit controller specific data that has been changed by any program and program specific data that has been changed only for completed programs to the secondary processor.

摘要翻译： 实现多任务操作系统的工业控制系统采用具有处理器和I / O数据表的主控制器和次控制器。 处理器被配置为执行一个或多个优先级排序的程序。 跟踪主处理器的I / O数据表中的变化用于独立跟踪已更改的控制器特定数据的更改和已更改的程序特定数据，并传输任何程序已更改的控制器特定数据 并且仅将已完成的程序改变为次要处理器的程序特定数据。

公开(公告)号：US20090125122A1

公开(公告)日：2009-05-14

申请号：US12242223

申请日：2008-09-30

申请人： William B. Cook ,  David A. Karpuszka

发明人： William B. Cook ,  David A. Karpuszka

IPC分类号： G05B15/02 ,  G05B9/03

CPC分类号： G05B9/03 ,  G05B19/058 ,  G05B2219/14131 ,  G05B2219/15079

摘要： An industrial control system implementing a multi-tasking operating system employs a primary and secondary controller each having a processor and an I/O data table. The processors are configured to execute one or more priority ranked programs. A tracking of changes in the I/O data table of the primary processor is used to independently track changes to controller specific data that has been changed and program specific data that has been changed and to transmit controller specific data that has been changed by any program and program specific data that has been changed only for completed programs to the secondary processor.

摘要翻译： 实现多任务操作系统的工业控制系统采用具有处理器和I / O数据表的主控制器和次控制器。 处理器被配置为执行一个或多个优先级排序的程序。 跟踪主处理器的I / O数据表中的变化用于独立跟踪已更改的控制器特定数据的更改和已更改的程序特定数据，并传输任何程序已更改的控制器特定数据 并且仅将已完成的程序改变为次要处理器的程序特定数据。

公开(公告)号：US5764927A

公开(公告)日：1998-06-09

申请号：US536533

申请日：1995-09-29

申请人： Timothy J. Murphy ,  Alan C. Cribbs ,  Robert C. Weppler ,  Margarita M. Hutz ,  Kendal R. Harris ,  Jack D. Calderon ,  David A. Karpuszka

发明人： Timothy J. Murphy ,  Alan C. Cribbs ,  Robert C. Weppler ,  Margarita M. Hutz ,  Kendal R. Harris ,  Jack D. Calderon ,  David A. Karpuszka

IPC分类号： G05B19/042 ,  G06F13/40 ,  H01J13/00

CPC分类号： G06F13/409 ,  G05B19/0423

摘要： A bus structure for interconnecting the modules of an industrial automation controller includes DATA lines and associated control lines that enable interface circuits on each module to transfer frames of data. Modules connected to the bus structure support data transfers of differing widths and differing speeds, and interface circuits within each module automatically adapt to data width and speed differences between communicating modules. During a first bus cycle of each transfer, sending and receiving modules negotiate a bus width and clock speed to be used for the transfer by asserting their respective width and speed codes onto a set of wired-or status lines. After the first bus cycle, the status lines are then used for communicating alternate functions between the participating modules.

摘要翻译： 用于互连工业自动化控制器的模块的总线结构包括DATA线和相关联的控制线，其使每个模块上的接口电路能够传输数据帧。 连接到总线结构的模块支持不同宽度和不同速度的数据传输，每个模块内的接口电路自动适应通信模块之间的数据宽度和速度差异。 在每个传输的第一个总线周期期间，发送和接收模块通过将其各自的宽度和速度代码断言到一组有线或状态线来协商用于传输的总线宽度和时钟速度。 在第一个总线周期之后，状态线用于在参与模块之间传递备用功能。