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1.发明授权System and method for coarse tuning a phase locked loop (PLL) synthesizer using 2-PI slip detection 有权使用2-PI滑移检测来粗调锁相环（PLL）合成器的系统和方法公开(公告)号：US06774732B1
公开(公告)日：2004-08-10
申请号：US10367007
申请日：2003-02-14
IPC分类号： H03L7085
摘要： A system for coarsely tuning at least one voltage controlled oscillator (VCO) (211) in a phase locked loop (PLL) synthesizer (200) that includes a phase-frequency detector (PFD) for determining a phase difference between a VCO frequency and a reference frequency and providing an error signal if the VCO frequency and reference frequency are at least 2&pgr; radians out of phase. A monitor (215) is then used for tracking the number of error signals produced by the PFD. The free running frequency of the VCO may be coarsely tuned in the event the monitor circuit reaches some predetermined level. The invention offers great advantage in enabling a PLL to be coarsely tuned to enable the PLL's VCO to remain with an operational range despite operational factors that effect circuit operation.
摘要翻译： 一种用于在锁相环（PLL）合成器（200）中粗调谐至少一个压控振荡器（VCO）（211）的系统，该系统包括用于确定VCO频率与VCO频率之间的相位差的相位 - 频率检测器（PFD） 参考频率，并且如果VCO频率和参考频率相位至少为2pi弧度，则提供误差信号。 然后使用监视器（215）来跟踪由PFD产生的误差信号的数量。 在监控电路达到某一预定水平的情况下，VCO的自由运行频率可能会被粗调。 本发明提供了极大的优点，即使PLL能够被粗调，以使PLL的VCO保持在操作范围，尽管影响电路操作的操作因素。
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公开(公告)号：US5491434A
公开(公告)日：1996-02-13
申请号：US349331
申请日：1994-12-05
摘要： A differential amplitude detection circuit (10) passes the positive and negative components of a data communication differential signal through peak detector circuits (12) and (26), respectively. The peak detected voltages are held at first (15) and second (37) nodes by holding capacitors (14) and (28). Current loads (18) and (30) sink predetermined currents from the first and second nodes to prevent the peak voltages from becoming accumulated by the holding capacitors. The peak detected voltages are summed by summing circuit (21) to provide a signal V.sub.OUT that is absent of DC offset voltage errors that were present in the originally transmitted data signal. First and second resistors (36, 38) extract the common mode component of the input signal which may be subtracted from the V.sub.OUT signal for providing an error free true data output signal VTO.
摘要翻译： 差分幅度检测电路（10）分别通过峰值检测器电路（12）和（26）传递数据通信差分信号的正和负分量。 峰值检测电压通过保持电容器（14）和（28）保持在第一（15）和第二（37）节点。 电流负载（18）和（30）吸收来自第一和第二节点的预定电流，以防止峰值电压被保持电容器累积。 峰值检测电压由求和电路（21）求和，以提供不存在于最初发送的数据信号中的DC偏移电压误差的信号VOUT。 第一和第二电阻器（36,38）提取可以从VOUT信号中减去的输入信号的共模分量，以提供无错误的真实数据输出信号VTO。
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公开(公告)号：US5015892A
公开(公告)日：1991-05-14
申请号：US494293
申请日：1990-03-16
申请人： Kaveh Parsi , David B. Harnishfeger
发明人： Kaveh Parsi , David B. Harnishfeger
CPC分类号： H03K5/135
摘要： A circuit for asynchronously delaying an input signal whereby the precision of the time delay is proportional to the precision of the clock. A first circuit is coupled across a first capacitor for charging the first capacitor to a predetermined voltage when the clock is in a first logic state and discharging the first capacitor when the clock is in a second logic state. A peak-hold circuit having an input coupled to a first terminal of the first capacitor and an output signal at an output that provides a reference voltage representative of the peak voltage occurring at the input of the peak-hold circuit which is a function of the time interval the clock occupied the first logic state. A second circuit is coupled across a second capacitor for charging the second capacitor when the input signal is in a first logic state, and discharging the second capacitor when the input signal is in a second logic state. Also, a comparator having a first input coupled to the output of the peak-hold circuit, a second input coupled to a first terminal of the second capacitor, and an output at which an output signal is provided that represents the input signal delayed by a predetermined time which is a function of the reference voltage.
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4.发明授权Two port voltage controlled oscillator for use in wireless personal area network synthesizers 有权两端口压控振荡器，用于无线个域网络合成器公开(公告)号：US06987423B2
公开(公告)日：2006-01-17
申请号：US10643310
申请日：2003-08-19
IPC分类号： H03L7/00
CPC分类号： H03B5/20
摘要： A voltage controlled oscillator (VCO) for use in a personal area network synthesizer includes a delay cell (100), a first current amplifier (201, 203) for amplifying an input current, a resister capacitor (RC) tuning network (207, 209, 211) for varying the amount of amplification and delay of an output of the first current amplifier. A second current amplifier (213, 215) is then used for amplifying an output current from the RC tuning network. The invention includes a unique composite voltage variable capacitor (CVVC) (300) for precisely tuning the amount of delay presented by the delay cell. The unique topology of the delay cell (100) allows it to be readily used in voltage controlled oscillators (VCOs) operable at frequencies above 1 GHz.
摘要翻译： 用于个人区域网络合成器的压控振荡器（VCO）包括延迟单元（100），用于放大输入电流的第一电流放大器（201,203），电阻电容器（RC）调谐网络（207,209） ，211），用于改变第一电流放大器的输出的放大量和延迟量。 然后，第二电流放大器（213,215）用于放大来自RC调谐网络的输出电流。 本发明包括用于精确调节由延迟单元呈现的延迟量的独特的复合电压可变电容器（CVVC）（300）。 延迟单元（100）的独特拓扑允许其容易地用于在1GHz以上的频率下工作的压控振荡器（VCO）。
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公开(公告)号：US4814635A
公开(公告)日：1989-03-21
申请号：US126135
申请日：1987-11-27
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/0944 , H03K5/24
CPC分类号： H03K19/09441 , H03K19/00384 , H03K19/018521
摘要： A voltage translator circuit generates a predetermined output voltage (e.g. one half of the supply voltage) in response to a predetermined input voltage. A pair of matched field effect transistors are coupled in series between first and second sources of supply voltage. The gate of the load transistor is coupled to a reference voltage, and the gate of the drive transistor is coupled to a source of input voltage. When both transistors are subject to the same operating conditions (at a predetermined input voltage level), their effective resistances become equal and the supply voltage is divided in half. The circuit does not depend for its operation upon precise threshold voltages of the devices as long as the devices are matched.
摘要翻译： 电压转换器电路响应于预定的输入电压产生预定的输出电压（例如电源电压的一半）。 一对匹配的场效应晶体管串联在第一和第二电源电压之间。 负载晶体管的栅极耦合到参考电压，并且驱动晶体管的栅极耦合到输入电压源。 当两个晶体管都处于相同的工作条件（在预定的输入电压电平）时，它们的有效电阻变得相等，电源电压被分成两半。 只要设备匹配，该电路不依赖于器件的精确阈值电压的操作。
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