公开(公告)号：US07456679B2

公开(公告)日：2008-11-25

申请号：US11416273

申请日：2006-05-02

申请人： John M. Pigott ,  Byron G. Bynum

发明人： John M. Pigott ,  Byron G. Bynum

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G05F3/30

摘要： A reference circuit includes: (a) a first reference circuit having a reference signal and a ΔVBE loop; and (b) a modification circuit using a first voltage to change a first current in the ΔVBE loop of the first reference circuit. In one embodiment, the reference circuit is a voltage reference circuit. In some embodiments, the reference circuit can include a bandgap core circuit, which adds a VBE and a multiplied ΔVBE, so that the output voltage of the reference circuit is a bandgap voltage. The reference circuit also can also include a modification circuit, which uses the output voltage (i.e. the reference signal) of the bandgap core circuit to change a current in the ΔVBE loop. The ΔVBE loop can be the portion of the circuit involved in generating the ΔVBE voltage. Other embodiments are disclosed in this application.

摘要翻译： 参考电路包括：（a）第一参考电路，具有参考信号和DeltaV 环路中的第一电流的修改电路。 在一个实施例中，参考电路是电压参考电路。 在一些实施例中，参考电路可以包括带隙核心电路，其添加一个V OUT和一个相乘的DeltaV BAT，使得参考电路的输出电压为 带隙电压。 参考电路还可以包括使用带隙核心电路的输出电压（即，参考信号）来改变DeltaV 环路中的电流的修改电路。 DeltaV 环路可以是生成ΔV电压所涉及的电路的部分。 在本申请中公开了其它实施例。

公开(公告)号：US4814635A

公开(公告)日：1989-03-21

申请号：US126135

申请日：1987-11-27

申请人： Gordon H. Allen ,  Byron G. Bynum ,  David B. Harnishfeger

发明人： Gordon H. Allen ,  Byron G. Bynum ,  David B. Harnishfeger

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/0944 ,  H03K5/24

CPC分类号： H03K19/09441 ,  H03K19/00384 ,  H03K19/018521

摘要： A voltage translator circuit generates a predetermined output voltage (e.g. one half of the supply voltage) in response to a predetermined input voltage. A pair of matched field effect transistors are coupled in series between first and second sources of supply voltage. The gate of the load transistor is coupled to a reference voltage, and the gate of the drive transistor is coupled to a source of input voltage. When both transistors are subject to the same operating conditions (at a predetermined input voltage level), their effective resistances become equal and the supply voltage is divided in half. The circuit does not depend for its operation upon precise threshold voltages of the devices as long as the devices are matched.

摘要翻译： 电压转换器电路响应于预定的输入电压产生预定的输出电压（例如电源电压的一半）。 一对匹配的场效应晶体管串联在第一和第二电源电压之间。 负载晶体管的栅极耦合到参考电压，并且驱动晶体管的栅极耦合到输入电压源。 当两个晶体管都处于相同的工作条件（在预定的输入电压电平）时，它们的有效电阻变得相等，电源电压被分成两半。 只要设备匹配，该电路不依赖于器件的精确阈值电压的操作。

公开(公告)号：US4677368A

公开(公告)日：1987-06-30

申请号：US915481

申请日：1986-10-06

申请人： Byron G. Bynum

发明人： Byron G. Bynum

IPC分类号： G05F3/30

CPC分类号： G05F3/30 ,  Y10S323/907

摘要： A circuit that develops a current having a predetermined temperature coefficient includes a pair of transistors which are supplied equal collector currents but which are operated at different current densities to produce a difference voltage between the emitters thereof that has a predetermined temperature coefficient. A third transistor is biased to sink a collector current the value of which is set by the ratio of the difference voltage to the value of a first resistor which is coupled between the collector and base of the third transistor. A second resistor can be coupled between the base and emitter of the third transistor to an output of the circuit whereby the current flowing from the output has a net temperature coefficient that is determined by the ratio of the value of the first resistor to the value of the second resistor.

摘要翻译： 产生具有预定温度系数的电流的电路包括一对晶体管，其提供相等的集电极电流，但是以不同的电流密度工作，以产生具有预定温度系数的发射极之间的差分电压。 第三晶体管被偏置以吸收集电极电流，其集合电流的值由差分电压与耦合在第三晶体管的集电极和基极之间的第一电阻器的值的比设置。 第二电阻器可以在第三晶体管的基极和发射极之间耦合到电路的输出，由此从输出端流出的电流具有由第一电阻器的值与第一电阻器的值的比值确定的净温度系数 第二个电阻。

公开(公告)号：US4553048A

公开(公告)日：1985-11-12

申请号：US582358

申请日：1984-02-22

申请人： Byron G. Bynum ,  David L. Cave

发明人： Byron G. Bynum ,  David L. Cave

IPC分类号： G05F3/30 ,  H03K17/082 ,  H03K17/14 ,  H03K17/30

CPC分类号： G05F3/30 ,  H03K17/0826 ,  H03K17/14

摘要： A thermal shut-down circuit is provided that is monolithically integrated in a power BIMOS process wherein a vertical power PNP output transistor comprises a P-type substrate as a collector. The circuit compensates for vertical currents injected from the P-substrate into lateral transistors. A first PNP transistor has an emitter connected to a first resistor and conducts a first current. A second PNP transistor has an emitter connected to a second resistor and conducts a second current. A third resistor has one terminal coupled to the emitter of the second transistor. A fourth resistor is coupled in series with an output means, the combination thereof being coupled in parallel with the second and third resistors.

摘要翻译： 提供了一种单片集成在功率BIMOS工艺中的热关断电路，其中垂直功率PNP输出晶体管包括作为集电极的P型衬底。 该电路补偿从P基板注入横向晶体管的垂直电流。 第一PNP晶体管具有连接到第一电阻器并且传导第一电流的发射极。 第二PNP晶体管具有连接到第二电阻器并且传导第二电流的发射极。 第三电阻器具有耦合到第二晶体管的发射极的一个端子。 第四电阻器与输出装置串联耦合，其组合与第二和第三电阻器并联耦合。

公开(公告)号：US4460865A

公开(公告)日：1984-07-17

申请号：US412691

申请日：1982-08-30

申请人： Byron G. Bynum ,  Randall C. Gray ,  Robert B. Jarrett

发明人： Byron G. Bynum ,  Randall C. Gray ,  Robert B. Jarrett

IPC分类号： G05F3/30 ,  G05F3/08

CPC分类号： G05F3/30 ,  Y10S323/907

摘要： A variable temperature coefficient level shifter includes a circuit which generates a voltage V.sub.BE having a negative temperature coefficient and a voltage .DELTA.V.sub.BE having a positive temperature coefficient. A control current is generated by placing a first resistor between V.sub.BE and ground and a second resistor between .DELTA.V.sub.BE and ground. Each of these currents forms a component of the control current which then has some net temperature coefficient. By properly scaling the resistors the control current may have any desired temperature coefficient between 2800 ppm and 3000 ppm. Once the temperature coefficient is set, a third resistor is provided through which the control current flows. The amplitude of the shift is then selected by selecting the value of resistor R.sub.S.

摘要翻译： 可变温度系数电平移位器包括产生具有负温度系数的电压VBE和具有正温度系数的电压DELTA VBE的电路。 通过在VBE和地之间放置第一个电阻器和在DELTA VBE和地之间放置第二个电阻器来产生控制电流。 这些电流中的每一个形成控制电流的分量，其然后具有一些净温度系数。 通过适当地缩放电阻器，控制电流可以具有在2800ppm和3000ppm之间的所需温度系数。 一旦设置了温度系数，就提供控制电流流过的第三个电阻。 然后通过选择电阻RS的值来选择偏移的幅度。

公开(公告)号：US09559592B2

公开(公告)日：2017-01-31

申请号：US13525882

申请日：2012-06-18

申请人： John M. Pigott ,  Byron G. Bynum ,  Geoffrey W. Perkins

发明人： John M. Pigott ,  Byron G. Bynum ,  Geoffrey W. Perkins

IPC分类号： H02M3/158 ,  H02M3/156 ,  H02M1/00

CPC分类号： H02M3/1588 ,  H02M3/156 ,  H02M3/1563 ,  H02M2001/0009 ,  Y02B70/1466

摘要： A DC-DC converter (100) includes a switching transistor (M0) connecting an input power terminal (VIN) to an inductor (114) that is also connected to an output power terminal (VOUT), a synchronous rectification transistor (M1) connected to a junction node (113) between the inductor (114) and the switching transistor (M0), and a synchronous rectifier control circuit (200) with an integration capacitor (226) having a voltage that is charged and discharged by first and second current sources (210, 220) to track the charging and discharging of the inductor current, thereby generating a synchronous rectifier control signal (SR) that is applied to the synchronous rectification transistor to discharge the inductor current to zero.

摘要翻译： DC-DC转换器（100）包括将输入电源端子（VIN）连接到也连接到输出电源端子（VOUT）的电感器（114）的开关晶体管（M0），连接到同步整流晶体管 耦合到电感器（114）和开关晶体管（M0）之间的结节点（113），以及具有积分电容器（226）的同步整流器控制电路（200），其具有通过第一和第二电流充电和放电的电压 源（210,220）来跟踪电感器电流的充电和放电，从而产生施加到同步整流晶体管以将电感器电流放电到零的同步整流器控制信号（SR）。

公开(公告)号：US4990863A

公开(公告)日：1991-02-05

申请号：US481268

申请日：1990-02-20

申请人： David M. Susak ,  Byron G. Bynum

发明人： David M. Susak ,  Byron G. Bynum

IPC分类号： H03F3/30

CPC分类号： H03F3/3067

摘要： An amplifier output stage with minimum circuitry and optimum performance for providing a SAT-to-SAT output voltage signal at an output terminal. The amplifier output stage includes a first transistor having a collector coupled to the output terminal for sourcing current thereto, a base coupled to a first supply voltage terminal, and an emitter coupled to the first supply voltage terminal. A second transistor having a collector coupled to the output terminal for sinking current thereat, a base, and an emitter coupled to a second supply voltage terminal. A third transistor having a collector, a base coupled to the base of the second transistor, and an emitter coupled to the second supply voltage terminal by a first resistor. A fourth transistor having a collector coupled to the first supply voltage terminal, a base coupled to an input terminal, and an emitter coupled to the base of the third transistor. A fifth transistor having a collector coupled to the base of the first transistor, a base coupled to the collector of the third transistor, and an emitter coupled to the second supply voltage terminal and a sixth transistor having a collector coupled to the first supply voltage terminal, a base coupled to the first supply voltage terminal and to the second supply voltage terminal, and an emitter coupled to the base of the fifth transistor.

摘要翻译： 放大器输出级，具有最小电路和最佳性能，可在输出端提供SAT至SAT输出电压信号。 放大器输出级包括第一晶体管，其具有耦合到输出端的集电极，用于向其提供电流，耦合到第一电源电压端的基极和耦合到第一电源电压端的发射极。 第二晶体管，其具有耦合到输出端的集电极，用于在其上吸收电流，基极和耦合到第二电源电压端的发射极。 具有集电极，耦合到第二晶体管的基极的基极和通过第一电阻耦合到第二电源电压端的发射极的第三晶体管。 具有耦合到第一电源电压端子的集电极的第四晶体管，耦合到输入端子的基极和耦合到第三晶体管的基极的发射极。 第五晶体管，其具有耦合到第一晶体管的基极的集电极，耦合到第三晶体管的集电极的基极和耦合到第二电源电压端子的发射极以及耦合到第一电源电压端子的集电极的第六晶体管 ，耦合到第一电源电压端子和第二电源电压端子的基极，以及耦合到第五晶体管的基极的发射极。

公开(公告)号：US4801825A

公开(公告)日：1989-01-31

申请号：US70284

申请日：1987-07-06

申请人： Michael E. Stanley ,  Walter V. Lowe ,  Byron G. Bynum

发明人： Michael E. Stanley ,  Walter V. Lowe ,  Byron G. Bynum

IPC分类号： H03K19/013 ,  H03K19/082 ,  H03K19/02 ,  H03K19/01

CPC分类号： H03K19/0826 ,  H03K19/0136

摘要： A circuit is provided which comprises a push-pull switching stage responsive to applied control signals for alternately establishing high and low output voltage levels at an output of the circuit responsive to control signals which are derived from an applied input logic signal and which is disabled in response to the control signals being disabled for providing a high output impedance at the output. The circuit includes circuitry responsive to an applied disable signal for disabling the control signals while enabling further circuitry, the latter providing a transient current path to improve the transition from the high voltage output level to the high output impedance condition while establishing a pseudo high output impedance at the output of the circuit until the push-pull stage is disabled.

摘要翻译： 提供了一种电路，其包括响应于施加的控制信号的推挽式开关级，用于响应于从施加的输入逻辑信号导出的控制信号在电路的输出处交替地建立高和低输出电压电平， 对控制信号的响应被禁用以在输出端提供高输出阻抗。 电路包括响应于施加的禁用信号的电路，用于禁用控制信号，同时启用另外的电路，后者提供瞬态电流路径，以改善从高电压输出电平向高输出阻抗状态的转变，同时建立伪高输出阻抗 在电路的输出端，直到推挽级被禁止。

公开(公告)号：US4521737A

公开(公告)日：1985-06-04

申请号：US582357

申请日：1984-02-22

申请人： Byron G. Bynum

发明人： Byron G. Bynum

IPC分类号： H03F3/72 ,  H03F3/16

CPC分类号： H03F3/72

摘要： An integrated current amplifier circuit combining bipolar and MOS technologies provides accurate current gain over a wide voltage supply range. The amplifier circuit includes a current source for providing first and second currents and first and second resistive circuits coupled to the current source for sinking the respective currents supplied therefrom. A feedback transistor connected between the current source and an output of the amplifier circuit provides current feedback to the first resistive circuit to establish the current gain action of the amplifier circuit which becomes a ratio of two resistors times an input current supplied to the second resistive circuit. The ratio of the two resistors can be accurately controlled thereby controlling the current gain of the amplifier circuit. Additionally, an active turn-off circuit requiring no standby bias current is provided to ensure that the feedback transistor is non-conducting when the amplifier is in an off state.

摘要翻译： 组合双极和MOS技术的集成电流放大器电路在宽电压电源范围内提供精确的电流增益。 放大器电路包括用于提供第一和第二电流的电流源以及耦合到电流源的第一和第二电阻电路，用于吸收从其提供的相应电流。 连接在电流源和放大器电路的输出端之间的反馈晶体管向第一电阻电路提供电流反馈以建立放大器电路的电流增益作用，该放大器电路成为两个电阻的比值乘以提供给第二电阻电路的输入电流 。 可以精确地控制两个电阻器的比例，从而控制放大器电路的电流增益。 另外，提供了不需要备用偏置电流的有源截止电路，以确保当放大器处于断开状态时反馈晶体管不导通。

公开(公告)号：US5479092A

公开(公告)日：1995-12-26

申请号：US388116

申请日：1995-02-13

申请人： John M. Pigott ,  Robert B. Jarrett ,  Byron G. Bynum

发明人： John M. Pigott ,  Robert B. Jarrett ,  Byron G. Bynum

IPC分类号： G05F1/46 ,  G05F3/30 ,  G05F3/20

CPC分类号： G05F1/463 ,  G05F3/30 ,  Y10S323/907

摘要： A correction circuit (12) for providing an error correction voltage for a voltage reference (11). The voltage reference (11) provides a reference voltage within a predetermined temperature range. The voltage reference prior to correction has a peak magnitude at a temperature T.sub.0 within the predetermined temperature range. A first circuit (13) generates a correction current. Zero current is provided by the first circuit (13) at T.sub.0. A second circuit (14) receives the correction current and provides an output current that is uni-directional or of the same sense above and below T.sub.0. [Means responsive to t] The output current of the second circuit (14) generates a voltage across a resistor (28) that is [combined] added to the reference voltage above and below T.sub.0.

摘要翻译： 一种用于为电压基准（11）提供纠错电压的校正电路（12）。 电压基准（11）在预定的温度范围内提供参考电压。 在校正之前的电压基准在预定温度范围内的温度T0具有峰值。 第一电路（13）产生校正电流。 零电流由第一电路（13）在T0提供。 第二电路（14）接收校正电流并提供在T0上方和下方是单向或相同感测的输出电流。 [响应于t的装置]第二电路（14）的输出电流产生一个电阻（28）上的电压，该电阻被[组合]加到高于和低于T0的参考电压上。