-
公开(公告)号:US20110004787A1
公开(公告)日:2011-01-06
申请号:US12865938
申请日:2009-02-09
CPC分类号: G06F11/08 , G06F15/7867 , G06F15/8023
摘要: An array of logic devices capable of self-determining the program, inputs and outputs from configuration information provided by its nearest neighbours. The rules used by each device to self-determine its behaviour are identical to those of every other device in the array. This facilitates the development of robust array configurations and robust behaviour of the device as a whole. This system's logic devices utilize three shift-registers, two are programmed before operation, the third is programmed on-the-fly by the other two. This facilitates a fast response to changes in the performance of the array in the event of partial dynamic or static failures of the array. An iterative design algorithm for the array ensures optimum use of the resources of the array.
摘要翻译: 能够自行确定程序的逻辑设备阵列,由其最邻近的邻居提供的配置信息的输入和输出。 每个设备用于自行确定其行为的规则与阵列中每个其他设备的规则相同。 这有助于开发强大的阵列配置和整个设备的鲁棒性能。 该系统的逻辑器件使用三个移位寄存器,两个在操作之前编程,第三个是由另外两个寄存器编程的。 这有助于在阵列的部分动态或静态故障的情况下快速响应阵列性能的变化。 阵列的迭代设计算法确保了数组资源的最佳使用。
-
公开(公告)号:US08386844B2
公开(公告)日:2013-02-26
申请号:US12865938
申请日:2009-02-09
CPC分类号: G06F11/08 , G06F15/7867 , G06F15/8023
摘要: An array of logic devices capable of self-determining the program, inputs and outputs from configuration information provided by its nearest neighbors. The rules used by each device to self-determine its behavior are identical to those of every other device in the array. This facilitates the development of robust array configurations and robust behavior of the device as a whole. This system's logic devices utilize three shift-registers, two are programmed before operation, the third is programmed on-the-fly by the other two. This facilitates a fast response to changes in the performance of the array in the event of partial dynamic or static failures of the array. An iterative design algorithm for the array ensures optimum use of the resources of the array.
摘要翻译: 能够自行确定程序的逻辑设备阵列,由其最邻近的邻居提供的配置信息的输入和输出。 每个设备用于自行确定其行为的规则与阵列中每个其他设备的规则相同。 这有助于开发强大的阵列配置和整个设备的鲁棒性能。 该系统的逻辑器件使用三个移位寄存器,两个在操作之前编程,第三个是由另外两个寄存器编程的。 这有助于在阵列的部分动态或静态故障的情况下快速响应阵列性能的变化。 阵列的迭代设计算法确保了数组资源的最佳使用。
-