公开(公告)号：US20060004975A1

公开(公告)日：2006-01-05

申请号：US10880830

申请日：2004-06-30

申请人： David Matheny

发明人： David Matheny

IPC分类号： G06F12/00

CPC分类号： G06F9/342

摘要： Methods, apparatus, and articles of manufacture to manage memory access are disclosed. An example method is used to detect a memory relocation process and disables memory access to a memory block in response to detecting the memory relocation process. The example method is then used to determine an absolute address value associated with the memory block. The absolute address value is then stored.

摘要翻译： 公开了用于管理存储器存取的方法，装置和制品。 响应于检测到存储器重定位过程，使用示例性方法来检测存储器重定位过程并且禁止对存储器块的存储器访问。 然后使用示例方法来确定与该存储器块相关联的绝对地址值。 然后存储绝对地址值。

公开(公告)号：US20050216715A1

公开(公告)日：2005-09-29

申请号：US10811533

申请日：2004-03-29

申请人： David Matheny ,  Eric Blair

发明人： David Matheny ,  Eric Blair

IPC分类号： G06F9/00 ,  G06F9/445

CPC分类号： G06F9/4416

摘要： A method includes receiving input from a user and, in response to the input, selecting one of a BCV (boot connection vector) pointer and a BEV (bootstrap entry vector) pointer to have a non-null value.

摘要翻译： 一种方法包括从用户接收输入，并且响应于该输入，选择BCV（引导连接向量）指针和BEV（引导条目向量）指针之一以具有非空值。

公开(公告)号：US2461386A

公开(公告)日：1949-02-08

申请号：US77989447

申请日：1947-10-15

申请人： DAVID MATHENY

发明人： DAVID MATHENY

IPC分类号： A63B57/00

CPC分类号： A63B57/357 ,  A63B57/40

公开(公告)号：US20050289288A1

公开(公告)日：2005-12-29

申请号：US10877763

申请日：2004-06-25

申请人： David Matheny ,  Navneet Malpani

发明人： David Matheny ,  Navneet Malpani

IPC分类号： G06F12/00 ,  H03M7/30

CPC分类号： H03M7/30

摘要： The inventive subject matter provides systems, methods, data structures, and software to compress and decompress a memory image such as an expansion read-only memory (ROM). Some embodiments include attaching a compressed memory image to a decompression shell to create a data structure that includes decompression instructions. Other embodiments include loading a memory image from a data structure by decompressing the memory image according to decompression instructions included in the data structure.

摘要翻译： 本发明主题提供了用于压缩和解压缩诸如扩展只读存储器（ROM）的存储器图像的系统，方法，数据结构和软件。 一些实施例包括将压缩的存储器映像附加到解压缩外壳以创建包括解压缩指令的数据结构。 其他实施例包括通过根据包括在数据结构中的解压缩指令解压缩存储器图像来从数据结构加载存储器映像。

公开(公告)号：US20180271188A1

公开(公告)日：2018-09-27

申请号：US15467723

申请日：2017-03-23

申请人： David Matheny ,  Tatiana Matheny

发明人： David Matheny ,  Tatiana Matheny

IPC分类号： A41D13/11

CPC分类号： A41D13/1169 ,  A41D2400/26

摘要： A nose mountable sunlight blocking assembly includes a panel that has a front side, a back side and a perimeter edge. The panel is comprised of a flexible material and is opaque such that the panel blocks UV radiation. An adhesive is positioned on and covers the back side of the panel. The panel is positioned on and covers an exposed upper surface of a nose such that at least 90% of the upper surface of the nose is covered by the panel.

公开(公告)号：US20060022520A1

公开(公告)日：2006-02-02

申请号：US11192545

申请日：2005-07-30

申请人： David Matheny

发明人： David Matheny

IPC分类号： B60T8/66

CPC分类号： B60Q1/448 ,  B60T8/17616

摘要： An exterior ABS alerting system takes the existing signal from the ABS ‘Electronic Brake Control Module’ that currently displays to the vehicle driver the activation of the ABS and sends that signal to an ‘exterior ABS alerting system. Once the exterior ABS alerting system receives this signal, the conventional rear brake lights can be strobed or could rapidly flash to alert oncoming and following vehicles of a braking duress by a vehicle. The braking indicator could simultaneously or sequentially strobe or fast flash to alert other drivers of emergency braking conditions. The exterior alerting module would only act in an over-ride capacity. Once the signal from the EBCM ceases, the exterior alert module ceases to override normal brake lamp operations.

摘要翻译： 外部ABS警报系统将ABS“电子制动器控制模块”的现有信号从当前显示给车辆驾驶员的ABS的激活，并将该信号发送到“外部ABS警报系统”。 一旦外部ABS报警系统接收到该信号，传统的后刹车灯可以被选通或者可以快速闪动，以警告车辆的制动胁迫的迎面而来和随后的车辆。 制动指示器可以同时或顺序选通或快速闪烁，以提醒其他驾驶员处于紧急制动条件。 外部警报模块只能以超载能力工作。 一旦来自EBCM的信号停止，外部警报模块将停止覆盖正常的制动灯操作。

公开(公告)号：US20060004982A1

公开(公告)日：2006-01-05

申请号：US10882483

申请日：2004-06-30

申请人： David Matheny

发明人： David Matheny

IPC分类号： G06F12/08

CPC分类号： G06F9/5016 ,  G06F9/4401 ,  G06F12/0292 ,  G06F12/0623

摘要： In some embodiments, the invention involves a system and method relating to switching to protected mode to access extended memory while executing instruction code that is designed for real mode memory access. In at least one embodiment, the present invention is intended to enable complex option-ROM code to be executed during pre-boot without corrupting system memory used by the BIOS or other option-ROMs. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，本发明涉及一种涉及在执行为实模式存储器访问设计的指令代码时切换到保护模式以访问扩展存储器的系统和方法。 在至少一个实施例中，本发明旨在使复杂的选项ROM代码在预引导期间被执行，而不会破坏由BIOS或其他选项ROM使用的系统存储器。 描述和要求保护其他实施例。

公开(公告)号：US07552319B2

公开(公告)日：2009-06-23

申请号：US10880830

申请日：2004-06-30

申请人： David Matheny

发明人： David Matheny

IPC分类号： G06F15/177

CPC分类号： G06F9/342

摘要： An example method involves detecting a memory relocation process and disabling memory access to a memory block in response to detecting the memory relocation process. The example method also involves determining an absolute address value associated with the memory block and storing the absolute address value.

摘要翻译： 示例性方法涉及检测存储器重定位过程并且响应于检测到存储器重定位过程而禁止对存储器块的存储器访问。 示例性方法还涉及确定与存储块相关联的绝对地址值并存储绝对地址值。

公开(公告)号：US20050251676A1

公开(公告)日：2005-11-10

申请号：US10839816

申请日：2004-05-05

申请人： Hemal Shah ,  David Matheny ,  Jeff Zachem

发明人： Hemal Shah ,  David Matheny ,  Jeff Zachem

IPC分类号： H04L9/00 ,  H04L29/06

CPC分类号： H04L63/12

摘要： A card receives data encoded in a protocol. The data may be divided into packets, or still in a protocol data unit. If still in a protocol data unit, the card divides the data into packets of appropriate size. Digests appropriate to the protocol are computed and inserted into the packets. Checksums are generated for the packets that need them, such as the packet now including the digest. The packets may then be transmitted to a recipient.

摘要翻译： 卡片接收协议中编码的数据。 数据可以被分成分组，或仍然在协议数据单元中。 如果仍然在协议数据单元中，则卡将数据分成适当大小的数据包。 计算适合于协议的摘要并将其插入到数据包中。 为需要它们的数据包生成校验和，例如现在包含摘要的数据包。 然后可以将分组发送到接收者。

公开(公告)号：US20050223129A1

公开(公告)日：2005-10-06

申请号：US10815961

申请日：2004-04-02

申请人： Tan Tran ,  Gerard Williams ,  David Matheny ,  David Flynn

发明人： Tan Tran ,  Gerard Williams ,  David Matheny ,  David Flynn

IPC分类号： G06F12/06 ,  G06F13/16 ,  G06F13/28 ,  G06F13/36

CPC分类号： G06F13/1657 ,  G06F13/28

摘要： A data processor core 10 comprising: a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory 120 associated with said data processor core; a data processing portion 12 operable to perform data processing operations; a read/write port 40 operable to transfer data from said processor core to at least two buses 75A, 75B said at least two buses being operable to provide data communication between said processor core 10 and said at least one memory 120, said at least one memory 120 comprising at least two portions 120A, 120B, each of said at least two buses 75A, 75B being operable to provide data access to respective ones of said at least two portions 120A, 120B; arbitration logic 110 associated with said read/write port 40; wherein said arbitration logic is operable to route a data access request requesting access of data in one portion of said at least one memory received from said memory access interface to one of said at least two buses providing access to said one portion of said at least one memory and to route a further data access request requesting access of data in a further portion of said at least one memory received from said data processing portion to a further one of said at least two buses providing access to said further portion of said at least one memory, said routing of said data access requests being performed during the same clock cycle.

摘要翻译： 一种数据处理器核心10，包括：存储器访问接口部分30，可操作以在外部数据源与与所述数据处理器核心相关联的至少一个存储器120之间执行数据传送操作; 数据处理部分12，用于执行数据处理操作; 读/写端口40，其可操作以将数据从所述处理器核传输到至少两个总线75A，75B，所述至少两个总线可操作以在所述处理器核心10和所述至少一个存储器120之间提供数据通信， 至少一个存储器120包括至少两个部分120A，120B，所述至少两个总线75A，75B中的每一个可操作以提供对所述至少两个部分120A，120B中的相应部分的数据访问; 与所述读/写端口40相关联的仲裁逻辑110; 其中所述仲裁逻辑可操作用于将请求数据访问的数据访问请求路由到从所述存储器访问接口接收的所述至少一个存储器的一部分中的数据访问到所述至少两个总线之一，提供对所述至少一个的所述一个部分的访问 存储器，并且路由进一步的数据访问请求，请求从所述数据处理部分接收的所述至少一个存储器的另一部分中的数据访问到所述至少两个总线中的另一个，提供对所述至少一个 存储器，所述数据访问请求的路由在相同的时钟周期期间执行。