摘要:
A circuit for use in a phase lock loop including a first phase detector to detect a first phase error between input signals, the first phase detector obtaining the first phase error during a first time period, a second phase detector to detect a second phase error between the input signals, the second phase detector obtaining the second phase error during a second time period, the second time period being longer than the first time period, and a compensation circuit to compensate the first phase error with a portion of the second phase error signal.
摘要:
A method and apparatus for implementing a noise generator in an integrated circuit read channel to optimize the performance of the signal channel. In the preferred embodiment resistors are used to generate noise. The noise source is buffered and the noise signal passes through a pre-amplifier stage. A differential current digital-to-analog converter controlled multiplier cell controls the amplitude of the noise signal. A switch connects the noise signal to a differential current output buffer, which is coupled to a signal channel.