公开(公告)号：US07994042B2

公开(公告)日：2011-08-09

申请号：US11924735

申请日：2007-10-26

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

IPC分类号： H01L21/00

CPC分类号： H01L21/76816 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

摘要翻译： 提供了反逆向工程技术。 一方面，提供了一种在绝缘层中形成至少一个特征的方法。 该方法包括以下步骤。 离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。 蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同 在植入区域外侧。 空隙填充有至少一种导体材料以在绝缘层中形成特征。

公开(公告)号：US08324102B2

公开(公告)日：2012-12-04

申请号：US13169248

申请日：2011-06-27

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

IPC分类号： H01L21/00

CPC分类号： H01L21/76816 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

摘要翻译： 提供了反逆向工程技术。 一方面，提供了一种在绝缘层中形成至少一个特征的方法。 该方法包括以下步骤。 离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。 蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同 在植入区域外侧。 空隙填充有至少一种导体材料以在绝缘层中形成特征。

公开(公告)号：US20100225380A1

公开(公告)日：2010-09-09

申请号：US12396512

申请日：2009-03-03

申请人： Louis L. Hsu ,  David W. Kruger ,  James S. Mason ,  Richard W. Oldrey

发明人： Louis L. Hsu ,  David W. Kruger ,  James S. Mason ,  Richard W. Oldrey

IPC分类号： H03K17/78

CPC分类号： H01L23/576 ,  H01L2224/48091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.

摘要翻译： 提供一种用于抵抗篡改的方法和防篡改电路，包括半导体芯片中的逆向工程，以及设置有被摄体电路的设计结构。 用于检测芯片篡改状态的感测装置由包括待保护电路的半导体芯片形成。 防篡改控制信号发生器耦合到感测单元，用于响应于检测到的芯片篡改状态产生防篡改控制信号。 功能操作禁止电路耦合到防篡改控制信号发生器，用于响应于防篡改控制信号而禁止要被保护的电路的功能操作。

公开(公告)号：US08089285B2

公开(公告)日：2012-01-03

申请号：US12396512

申请日：2009-03-03

申请人： Louis L. Hsu ,  David W. Kruger ,  James S. Mason ,  Richard W. Oldrey

发明人： Louis L. Hsu ,  David W. Kruger ,  James S. Mason ,  Richard W. Oldrey

IPC分类号： G01R31/02 ,  G01R31/26 ,  G06F12/14 ,  G06F7/04

CPC分类号： H01L23/576 ,  H01L2224/48091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.

摘要翻译： 提供一种用于抵抗篡改的方法和防篡改电路，包括半导体芯片中的逆向工程，以及设置有被摄体电路的设计结构。 用于检测芯片篡改状态的感测装置由包括待保护电路的半导体芯片形成。 防篡改控制信号发生器耦合到感测单元，用于响应于检测到的芯片篡改状态产生防篡改控制信号。 功能操作禁止电路耦合到防篡改控制信号发生器，用于响应于防篡改控制信号而禁止要被保护的电路的功能操作。

公开(公告)号：US20110256720A1

公开(公告)日：2011-10-20

申请号：US13169248

申请日：2011-06-27

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

IPC分类号： H01L21/28

CPC分类号： H01L21/76816 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

摘要翻译： 提供了反逆向工程技术。 一方面，提供了一种在绝缘层中形成至少一个特征的方法。 该方法包括以下步骤。 离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。 蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同 在植入区域外侧。 空隙填充有至少一种导体材料以在绝缘层中形成特征。

公开(公告)号：US20090111257A1

公开(公告)日：2009-04-30

申请号：US11924735

申请日：2007-10-26

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

摘要翻译： 提供了反逆向工程技术。 一方面，提供了一种在绝缘层中形成至少一个特征的方法。 该方法包括以下步骤。 离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。 蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同 在植入区域外侧。 空隙填充有至少一种导体材料以在绝缘层中形成特征。