公开(公告)号：US09294099B2

公开(公告)日：2016-03-22

申请号：US14141458

申请日：2013-12-27

Applicant: Rohit Goyal ,  Deepak Kumar Behera ,  Naman Gupta

Inventor： Rohit Goyal ,  Deepak Kumar Behera ,  Naman Gupta

IPC: H03K21/00 ,  H03K23/58 ,  H03K19/00 ,  H03K21/10 ,  H03K21/12

CPC classification number: H03K23/588 ,  H03K19/0008 ,  H03K21/10 ,  H03K21/12 ,  H03K23/58

Abstract: A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.

Abstract translation: 混合计数器产生多位混合计数器值。 混合计数器包括两个或多个异步计数器，每个异步计数器被配置为生成多比特混合计数器值的比特的子集。 异步计数器由逻辑门和时钟门控电路互连。 逻辑门根据以前的异步计数器产生的位产生异步逻辑值。 时钟门控电路重新计时异步逻辑值以产生用于切换下一个异步计数器的同步逻辑值。 混合计数器的功能比传统的异步计数器更精确，功耗比传统的同步计数器少。

公开(公告)号：US20150188546A1

公开(公告)日：2015-07-02

申请号：US14141458

申请日：2013-12-27

Applicant: Rohit Goyal ,  Deepak Kumar Behera ,  Naman Gupta

Inventor： Rohit Goyal ,  Deepak Kumar Behera ,  Naman Gupta

IPC: H03K23/58 ,  H03K3/012 ,  H03K21/10

CPC classification number: H03K23/588 ,  H03K19/0008 ,  H03K21/10 ,  H03K21/12 ,  H03K23/58

Abstract: A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.

Abstract translation: 混合计数器产生多位混合计数器值。 混合计数器包括两个或多个异步计数器，每个异步计数器被配置为生成多比特混合计数器值的比特的子集。 异步计数器由逻辑门和时钟门控电路互连。 逻辑门根据以前的异步计数器产生的位产生异步逻辑值。 时钟门控电路重新计时异步逻辑值以产生用于切换下一个异步计数器的同步逻辑值。 混合计数器的功能比传统的异步计数器更精确，功耗比传统的同步计数器少。