公开(公告)号：US06184807B2

公开(公告)日：2001-02-06

申请号：US09123334

申请日：1998-07-28

申请人： Tony S. El-Kik ,  Dennis A. Brooks ,  Richard Muscavage

发明人： Tony S. El-Kik ,  Dennis A. Brooks ,  Richard Muscavage

IPC分类号： H03M712

CPC分类号： H03M5/12 ,  H03K5/1252 ,  H03K7/06 ,  H04L25/4904

摘要： An encoder which includes a flip-flop; a first, second and third NAND gate; a first and second inverter; and a first and second delay cell. The first inverter couples the flip-flop with the first NAND gate. The first delay cell couples the first NAND gate with the third NAND gate. The second inverter couples the second delay cell with the second NAND gate. Further, the second NAND gate couples the second inverter with the third NAND gate. The third NAND gate of the encoder produces a glitch-free encoded signal.

摘要翻译： 一种包括触发器的编码器; 第一，第二和第三NAND门; 第一和第二逆变器; 以及第一和第二延迟单元。 第一个反相器将触发器与第一个NAND门耦合。 第一延迟单元将第一NAND门与第三NAND门耦合。 第二反相器将第二延迟单元与第二NAND门耦合。 此外，第二NAND门将第二反相器与第三NAND门耦合。 编码器的第三个“与非”门产生无毛刺编码信号。

公开(公告)号：US06282666B1

公开(公告)日：2001-08-28

申请号：US09257954

申请日：1999-02-26

申请人： Laurence Edward Bays ,  Richard Muscavage ,  Dennis A. Brooks ,  Xingdong Dai ,  Eric Wilcox

发明人： Laurence Edward Bays ,  Richard Muscavage ,  Dennis A. Brooks ,  Xingdong Dai ,  Eric Wilcox

IPC分类号： G06F1202

CPC分类号： G06F1/3253 ,  G06F1/3203 ,  Y02D10/151

摘要： A computer peripheral device suitable for operation with a Peripheral Component Interconnect (PCI) Bus or the like, has the ability to “wakeup” the bus from a cold state (e.g., D3cold) without the need to supply auxiliary power (e.g., 3.3 volts) to the entire device during the cold state. A modem in the preferred embodiment (although the invention is applicable to other peripheral devices), the device latches device status information from the main circuitry of the device (operating on 5 volts, for example) into a “keep alive” circuit connected to the auxiliary power supply upon the falling edge of a PCI reset signal (RST#). Additionally, the auxiliary power supply also powers a ring detect circuit for the detection of an incoming telephone call, which incoming call triggers a Power Management Event (PME#) signal for changing the state of the bus to an active state. Further, the auxiliary power supply powers a RST# detection circuit for indicating that a change in the power state of the bus is imminent.

摘要翻译： 适用于使用外围组件互连（PCI）总线等的计算机外围设备具有从总线“冷却”（例如，D3cold）唤醒总线的能力，而不需要提供辅助电源（例如，3.3伏特 ）在冷态期间到整个设备。 在优选实施例中的调制解调器（尽管本发明可应用于其他外围设备），设备将来自设备的主电路（例如，在5伏特上工作）的设备状态信息锁定到连接到 辅助电源在PCI复位信号（RST＃）的下降沿。 此外，辅助电源还为环路检测电路供电以检测进入的电话呼叫，该来电呼叫触发电力管理事件（PME＃）信号，以将总线的状态改变为活动状态。 此外，辅助电源为RST＃检测电路供电，用于指示总线的功率状态的改变即将到来。

公开(公告)号：US06377086B1

公开(公告)日：2002-04-23

申请号：US09412491

申请日：1999-10-05

申请人： Laurence E. Bays ,  Dennis A. Brooks ,  Xingdong Dai ,  Richard Muscavage

发明人： Laurence E. Bays ,  Dennis A. Brooks ,  Xingdong Dai ,  Richard Muscavage

IPC分类号： H03B100

CPC分类号： H03K19/018521

摘要： A fully-static dual-voltage sense circuit designed for a mixed-voltage system senses the power-rail voltage of other devices that the device is interfaced with, and achieves a low-power consumption level without software assistance when the sensing circuit is active, and protects low-voltage process devices in the circuit from possible high voltage damage at the interface. In a preferred embodiment, the present invention includes an integrated circuit having a dual-voltage sense circuit, the sense circuit including a sense circuit input node supplied with an input voltage Vin; a sense circuit power input node supplied with a power-supply voltage; and a sense circuit output node outputting a digital signal of a voltage level equal to or less than the voltage level of a low-voltage digital signal, regardless of the voltage level of the input voltage.

摘要翻译： 设计用于混合电压系统的全静态双电压检测电路可以感测到器件接口的其他器件的电源电压，并且在感测电路处于活动状态时，无需软件辅助即可实现低功耗级别， 并保护电路中的低压工艺装置免受接口处的高压损坏。 在优选实施例中，本发明包括具有双电压检测电路的集成电路，感测电路包括提供有输入电压Vin的感测电路输入节点; 提供有电源电压的感测电路电力输入节点; 以及感测电路输出节点，输出等于或小于低电压数字信号的电压电平的电压电平的数字信号，而与输入电压的电压电平无关。