公开(公告)号：US20130339593A1

公开(公告)日：2013-12-19

申请号：US13523523

申请日：2012-06-14

申请人： Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

发明人： Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0864 ,  G06F9/3824 ,  G06F12/0846 ,  G06F12/0855 ,  Y02D10/13

摘要： A computer program product for reducing penalties for cache accessing operations is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes respectively associating platform registers with cache arrays, loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, and, based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays.

摘要翻译： 提供了用于减少高速缓存访​​问操作的惩罚的计算机程序产品。 计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。 该方法包括分别将平台寄存器与高速缓存阵列相关联，将控制信息和关于一个或多个高速缓存阵列执行的存储操作的数据加载到分别与一个或多个缓存阵列中的一个或多个 缓存阵列，并且基于一个或多个缓存阵列变得可用，使用来自相同平台寄存器的控制信息将一个或多个平台寄存器中的数据提交到一个或多个缓存阵列。

公开(公告)号：US09378023B2

公开(公告)日：2016-06-28

申请号：US13495201

申请日：2012-06-13

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Edward J. Kaminski, Jr. ,  Diane L. Orf

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Edward J. Kaminski, Jr. ,  Diane L. Orf

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F13/16 ,  G06F13/18 ,  G06F9/54 ,  G06F13/14

CPC分类号： G06F9/3836 ,  G06F9/3869 ,  G06F9/544 ,  G06F13/14 ,  G06F13/1605 ,  G06F13/1615 ,  G06F13/1621 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663

摘要： Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first pipeline and a second subrequest for the second pipeline. Another aspect includes completing the first subrequest by the first pipeline. Another aspect includes, based on completing the first subrequest by the first pipeline, sending cross-pipe unlock signal from the first pipeline to the second pipeline. Yet another aspect includes, based on receiving the cross-pipe unlock signal by the second pipeline, completing the second subrequest by the second pipeline.

公开(公告)号：US20130339701A1

公开(公告)日：2013-12-19

申请号：US13495201

申请日：2012-06-13

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Edward J. Kaminski,, JR. ,  Diane L. Orf

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Edward J. Kaminski,, JR. ,  Diane L. Orf

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3869 ,  G06F9/544 ,  G06F13/14 ,  G06F13/1605 ,  G06F13/1615 ,  G06F13/1621 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663

摘要： Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first pipeline and a second subrequest for the second pipeline. Another aspect includes completing the first subrequest by the first pipeline. Another aspect includes, based on completing the first subrequest by the first pipeline, sending cross-pipe unlock signal from the first pipeline to the second pipeline. Yet another aspect includes, based on receiving the cross-pipe unlock signal by the second pipeline, completing the second subrequest by the second pipeline.

摘要翻译： 实施例涉及用于多管线计算机处理器的跨管道串行化。 一个方面包括由处理器接收处理器，该处理器包括第一流水线，第一流水线包括串行化流水线和第二流水线，第二流水线包括非串行流水线，包括第一流水线的第一子请求的请求和 第二个管道的第二个子请求。 另一方面包括通过第一管道完成第一个子请求。 另一方面包括，基于通过第一管道完成第一子请求，将第一管道的跨管解锁信号发送到第二管道。 另一方面包括，基于通过第二管线接收横管解锁信号，通过第二管道完成第二子请求。

公开(公告)号：US20130339606A1

公开(公告)日：2013-12-19

申请号：US13523567

申请日：2012-06-14

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

IPC分类号： G06F12/08

CPC分类号： G06F12/0806 ,  G06F9/38 ,  G06F9/3855 ,  G06F12/0855 ,  G11C7/22 ,  G11C2207/229 ,  Y02D10/13

摘要： A computer product for reducing store operation busy times is provided and relates to associating first and second platform registers with a cache array, determining that first and second store operations target a same wordline of the cache array, loading control information and data of the store operations into the platform registers and delaying a commit of the first store operation until the loading of the second platform register is complete. The method further includes committing the data from the platform registers using the control information from the platform registers to the wordline of the cache array at a same time to thereby reduce a busy time of the wordline of the cache array.

摘要翻译： 提供了用于减少存储操作繁忙时间的计算机产品，并且涉及将第一和第二平台寄存器与高速缓存阵列相关联，确定第一和第二存储操作针对高速缓存阵列的相同字线，加载控制信息和存储操作的数据 进入平台寄存器并延迟第一个存储操作的提交，直到第二个平台寄存器的加载完成。 该方法还包括使用来自平台寄存器的控制信息将来自平台寄存器的数据同时提交到高速缓存阵列的字线，从而减少高速缓存阵列的字线的繁忙时间。

公开(公告)号：US09075727B2

公开(公告)日：2015-07-07

申请号：US13523523

申请日：2012-06-14

申请人： Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

发明人： Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

IPC分类号： G06F12/08 ,  G06F9/38

CPC分类号： G06F12/0864 ,  G06F9/3824 ,  G06F12/0846 ,  G06F12/0855 ,  Y02D10/13

摘要： A computer program product for reducing penalties for cache accessing operations is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes respectively associating platform registers with cache arrays, loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, and, based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays.

公开(公告)号：US09015423B2

公开(公告)日：2015-04-21

申请号：US13523567

申请日：2012-06-14

申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F9/38 ,  G11C7/22

CPC分类号： G06F12/0806 ,  G06F9/38 ,  G06F9/3855 ,  G06F12/0855 ,  G11C7/22 ,  G11C2207/229 ,  Y02D10/13

摘要： A computer product for reducing store operation busy times is provided and relates to associating first and second platform registers with a cache array, determining that first and second store operations target a same wordline of the cache array, loading control information and data of the store operations into the platform registers and delaying a commit of the first store operation until the loading of the second platform register is complete. The method further includes committing the data from the platform registers using the control information from the platform registers to the wordline of the cache array at a same time to thereby reduce a busy time of the wordline of the cache array.

摘要翻译： 提供了用于减少存储操作繁忙时间的计算机产品，并且涉及将第一和第二平台寄存器与高速缓存阵列相关联，确定第一和第二存储操作针对高速缓存阵列的相同字线，加载控制信息和存储操作的数据 进入平台寄存器并延迟第一个存储操作的提交，直到第二个平台寄存器的加载完成。 该方法还包括使用来自平台寄存器的控制信息将来自平台寄存器的数据同时提交到高速缓存阵列的字线，从而减少高速缓存阵列的字线的繁忙时间。