公开(公告)号：US20060125028A1

公开(公告)日：2006-06-15

申请号：US11012413

申请日：2004-12-15

申请人： Chien-Hao Chen ,  Donald Chao ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Donald Chao ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L29/7833 ,  H01L29/6659 ,  H01L29/7843

摘要： A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.

摘要翻译： 提供了具有局部应力源的金属氧化物半导体场效应晶体管（MOSFET）。 根据本发明的实施例，晶体管包括源/漏区上的高应力膜，但不在栅电极上。 高应力膜可以是用于n沟道器件的拉伸应力膜或用于p沟道器件的压应力膜。 在源极/漏极区域上制造具有局部应力源的MOSFET的方法包括形成具有栅电极和源/漏区的晶体管，在栅电极和源/漏区上形成高应力膜，然后除去 高应力膜位于栅电极之上，从而使高应力膜位于源极/漏极区之上。 接触蚀刻停止层可以形成在晶体管上。

公开(公告)号：US20060246672A1

公开(公告)日：2006-11-02

申请号：US11119522

申请日：2005-04-29

申请人： Chien-Hao Chen ,  Donald Chao ,  Tze-Liang Lee

发明人： Chien-Hao Chen ,  Donald Chao ,  Tze-Liang Lee

IPC分类号： H01L21/336 ,  H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L29/78 ,  H01L29/7843

摘要： A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device having sidewall spacers. A highly stressed layer is deposited over the device. The stress is selectively adjusted in that portion of the layer over the gate electrode and the sidewall spacers. Preferably, the stress layer over the gate electrode and over the sidewall spacers is adjusted from a first stress to a second stress, wherein the first stress is one of tensile and compressive, and the second stress is the other of tensile and compressive. Preferred embodiments selectively induce a suitable stress within PMOS and NMOS channel regions for improving their respective carrier mobility. Still other embodiments of the invention comprise a field effect transistor (FET) having a overlying stressed layer, the stressed layer being comprised of different stress regions.

摘要翻译： 本发明的优选实施例提供半导体制造方法。 一个实施例包括形成具有侧壁间隔物的MOS器件。 高应力层沉积在器件上。 在栅极电极和侧壁间隔物上的层的该部分中选择性地调节应力。 优选地，栅极上方和侧壁间隔物上的应力层从第一应力调整到第二应力，其中第一应力是拉伸和压缩之一，第二应力是拉伸和压缩中的另一个。 优选实施例在PMOS和NMOS沟道区域内选择性地诱发适当的应力，以改善它们各自的载流子迁移率。 本发明的其它实施例包括具有上覆应力层的场效应晶体管（FET），所述应力层由不同的应力区域组成。

公开(公告)号：US20060267106A1

公开(公告)日：2006-11-30

申请号：US11137495

申请日：2005-05-26

申请人： Donald Chao ,  Chien-Hao Chen ,  Ling-Yen Yeh ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Donald Chao ,  Chien-Hao Chen ,  Ling-Yen Yeh ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/772

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device includes a substrate, a gate structure over the substrate, a first sidewall spacer on a sidewall of the gate structure, a first diffusion region in the substrate and adjacent to the gate structure, the first sidewall spacer and the first diffusion region being on one side of the gate structure, and a first conductive layer in the first diffusion region, the first conductive layer being spaced apart from the first sidewall spacer.

摘要翻译： 半导体器件包括衬底，衬底上的栅极结构，栅极结构的侧壁上的第一侧壁间隔物，衬底中的第一扩散区域和栅极结构附近，第一侧壁间隔物和第一扩散区域是 在所述栅极结构的一侧，以及所述第一扩散区域中的第一导电层，所述第一导电层与所述第一侧壁间隔物间隔开。