公开(公告)号：US20170278863A1

公开(公告)日：2017-09-28

申请号：US15470952

申请日：2017-03-28

申请人： YOUNG-SAN CHA ,  DONGKYU YOUN ,  TAE-SUNG KIM

发明人： YOUNG-SAN CHA ,  DONGKYU YOUN ,  TAE-SUNG KIM

IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/1157

摘要： A semiconductor device includes a substrate including a cell array region and a peripheral circuit region. The semiconductor device further includes a cell array disposed in the cell array region and including a plurality of cell strings connected to a bit line. The bit line extends in a first direction. The semiconductor device additionally includes a first cell row disposed in the peripheral circuit region and including a plurality of first cells arranged in a second direction crossing the first direction. The first and second directions being parallel to an upper surface of the substrate. The semiconductor device further includes a plurality of first interconnect lines each having a longitudinal axis in the first direction and connected to the plurality of first cells, and a plurality of first power lines extending in the second direction and connected to the plurality of first cells through the first interconnect lines.

公开(公告)号：US08531879B2

公开(公告)日：2013-09-10

申请号：US13080197

申请日：2011-04-05

申请人： Sangwon Hwang ,  DongKyu Youn ,  Jong-Nam Baek ,  Su Chang Jeon

发明人： Sangwon Hwang ,  DongKyu Youn ,  Jong-Nam Baek ,  Su Chang Jeon

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427 ,  G11C2216/14

摘要： A semiconductor memory device including a flash memory that includes a page, wherein the page includes a plurality of memory cells connected to even bitlines and odd bitlines of the flash memory, and the memory cells are disposed in a plurality of sectors. The semiconductor memory device also includes a memory controller configured to provide the flash memory with a read address that identifies sectors to be read. The flash memory is configured to determine a sequence of even sensing and odd sensing based on the read address and perform the even sensing and the odd sensing according to the determined sequence. In addition, the flash memory is configured to sense data of at least one identified sector that includes memory cells connected to the even bitlines during the even sensing and sense data of at least one identified sector that includes memory cells connected to the odd bitlines during the odd sensing.

摘要翻译： 一种包括闪存的半导体存储器件，包括页面，其中所述页面包括连接到所述闪速存储器的偶数位线和奇数位线的多个存储单元，并且所述存储器单元设置在多个扇区中。 半导体存储器件还包括存储器控制器，其被配置为向闪速存储器提供识别要读取的扇区的读地址。 闪速存储器被配置为基于读取地址确定偶数检测和奇数检测的顺序，并根据确定的顺序执行偶检测和奇检测。 另外，闪速存储器被配置为感测至少一个识别的扇区的数据，该数据包括在偶数感测期间连接到偶位线的存储器单元的数据，并且感测至少一个所识别的扇区的数据，该数据包括连接到奇数位线的存储器单元 奇感。

公开(公告)号：US20110286270A1

公开(公告)日：2011-11-24

申请号：US13080197

申请日：2011-04-05

申请人： Sangwon Hwang ,  DongKyu Youn ,  Jong-Nam Baek ,  Su Chang Jeon

发明人： Sangwon Hwang ,  DongKyu Youn ,  Jong-Nam Baek ,  Su Chang Jeon

IPC分类号： G11C14/00 ,  G11C16/26

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427 ,  G11C2216/14

摘要： A semiconductor memory device including a flash memory that includes a page, wherein the page includes a plurality of memory cells connected to even bitlines and odd bitlines of the flash memory, and the memory cells are disposed in a plurality of sectors. The semiconductor memory device also includes a memory controller configured to provide the flash memory with a read address that identifies sectors to be read. The flash memory is configured to determine a sequence of even sensing and odd sensing based on the read address and perform the even sensing and the odd sensing according to the determined sequence. In addition, the flash memory is configured to sense data of at least one identified sector that includes memory cells connected to the even bitlines during the even sensing and sense data of at least one identified sector that includes memory cells connected to the odd bitlines during the odd sensing.

摘要翻译： 一种包括闪存的半导体存储器件，包括页面，其中所述页面包括连接到所述闪速存储器的偶数位线和奇数位线的多个存储单元，并且所述存储器单元设置在多个扇区中。 半导体存储器件还包括存储器控制器，其被配置为向闪速存储器提供识别要读取的扇区的读地址。 闪速存储器被配置为基于读取地址确定偶数检测和奇数检测的顺序，并根据确定的顺序执行偶检测和奇检测。 另外，闪速存储器被配置为感测至少一个识别的扇区的数据，该数据包括在偶数感测期间连接到偶位线的存储器单元的数据，并且感测至少一个所识别的扇区的数据，该数据包括连接到奇数位线的存储器单元 奇感。