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    STACKED MEMORY CHIP HAVING REDUCED INPUT-OUTPUT LOAD, MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME
    2.
    发明申请
    STACKED MEMORY CHIP HAVING REDUCED INPUT-OUTPUT LOAD, MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME 有权
    具有减少的输入输出负载的堆叠存储芯片，包括其的存储模块和存储器系统

    公开(公告)号：US20160181214A1

    公开(公告)日：2016-06-23

    申请号：US14960909

    申请日：2015-12-07

    申请人： Ki-Seok OH ,  Doo-Hee HWANG ,  Dong-Yang LEE ,  Jong-Hyun CHOI

    发明人： Ki-Seok OH ,  Doo-Hee HWANG ,  Dong-Yang LEE ,  Jong-Hyun CHOI

    IPC分类号： H01L23/00 ,  H01L27/18 ,  H01L25/065

    CPC分类号： H01L24/06 ,  G11C7/1051 ,  G11C7/1078 ,  G11C2207/105 ,  H01L25/0657 ,  H01L27/18 ,  H01L27/222 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L2224/09515 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/1434

    摘要： A stacked memory chip includes a chip input-output pad unit, a first semiconductor die and a second semiconductor die. The chip input-output pad unit includes a chip command-address pad unit, a lower chip data pad unit and an upper chip data pad unit that are to be connected to an external device. The first semiconductor die electrically is connected to the chip command-address pad unit and the lower chip data pad unit and electrically disconnected from the upper chip data pad unit. The second semiconductor die electrically is connected to the chip command-address pad unit and the upper chip data pad unit and electrically disconnected from the lower chip data pad unit. The input-output load may be reduced by selectively connecting each of the stacked semiconductor dies to one of the lower chip data pad unit and the upper chip data pad unit.

    摘要翻译： 堆叠式存储器芯片包括芯片输入 - 输出焊盘单元，第一半导体管芯和第二半导体管芯。 芯片输入输出焊盘单元包括要连接到外部设备的芯片命令地址焊盘单元，下部芯片数据焊盘单元和上部芯片数据焊盘单元。 第一半导体管芯电连接到芯片命令地址焊盘单元和下部芯片数据焊盘单元，并与上部芯片数据焊盘单元电气断开。 第二半导体管芯电连接到芯片命令地址焊盘单元和上部芯片数据焊盘单元，并与下部芯片数据焊盘单元电气断开。 可以通过选择性地将每个堆叠的半导体管芯连接到下部芯片数据焊盘单元和上部芯片数据焊盘单元之一来减小输入输出负载。