公开(公告)号：US09818707B2

公开(公告)日：2017-11-14

申请号：US14960909

申请日：2015-12-07

申请人： Ki-Seok Oh ,  Doo-Hee Hwang ,  Dong-Yang Lee ,  Jong-Hyun Choi

发明人： Ki-Seok Oh ,  Doo-Hee Hwang ,  Dong-Yang Lee ,  Jong-Hyun Choi

IPC分类号： H01L23/52 ,  H01L23/00 ,  H01L25/065 ,  H01L27/18 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24 ,  G11C7/10

CPC分类号： H01L24/06 ,  G11C7/1051 ,  G11C7/1078 ,  G11C2207/105 ,  H01L25/0657 ,  H01L27/18 ,  H01L27/222 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L2224/09515 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/1434

摘要： A stacked memory chip includes a chip input-output pad unit, a first semiconductor die and a second semiconductor die. The chip input-output pad unit includes a chip command-address pad unit, a lower chip data pad unit and an upper chip data pad unit that are to be connected to an external device. The first semiconductor die electrically is connected to the chip command-address pad unit and the lower chip data pad unit and electrically disconnected from the upper chip data pad unit. The second semiconductor die electrically is connected to the chip command-address pad unit and the upper chip data pad unit and electrically disconnected from the lower chip data pad unit. The input-output load may be reduced by selectively connecting each of the stacked semiconductor dies to one of the lower chip data pad unit and the upper chip data pad unit.

公开(公告)号：US20110125982A1

公开(公告)日：2011-05-26

申请号：US12909031

申请日：2010-10-21

申请人： Jang-Seok Choi ,  Dong-Yang Lee ,  Joon Kun Kim

发明人： Jang-Seok Choi ,  Dong-Yang Lee ,  Joon Kun Kim

IPC分类号： G06F12/06

CPC分类号： G06F12/0653 ,  G06F11/073 ,  G06F11/0793 ,  G06F13/1668 ,  G11C5/02 ,  G11C5/04 ,  G11C8/12 ,  G11C11/408

摘要： A memory controller includes a memory capacity setting circuit and an address selecting circuit. The memory capacity setting circuit is configured to set a valid memory capacity of a memory device based on a defective cell information signal, and generate a valid memory capacity signal based on the valid memory capacity. The address selecting circuit is configured to disable an address signal corresponding to a memory block having a defective cell, and generate a selection address signal based on the valid memory capacity signal and the disabled address signal. A non-defective cell in a memory cell array is activated based on the selection address signal and a command signal.

摘要翻译： 存储器控制器包括存储器容量设置电路和地址选择电路。 存储器容量设置电路被配置为基于有缺陷的单元信息信号来设置存储器件的有效存储器容量，并且基于有效存储器容量生成有效存储器容量信号。 地址选择电路被配置为禁用与具有缺陷单元的存储块相对应的地址信号，并且基于有效存储器容量信号和禁用的地址信号生成选择地址信号。 存储单元阵列中的无缺陷单元基于选择地址信号和命令信号被激活。

公开(公告)号：US07478208B2

公开(公告)日：2009-01-13

申请号：US11546625

申请日：2006-10-12

申请人： Joon-Kun Kim ,  Dong-Yang Lee

发明人： Joon-Kun Kim ,  Dong-Yang Lee

IPC分类号： G06F13/00

CPC分类号： G11C5/06 ,  G11C7/1045

摘要： Semiconductor memory devices are provided. The semiconductor memory device includes a command decoder, a code converter and a code outputting unit. The command decoder is configured to receive a plurality of command signals from an external source, decode the plurality of command signals and generate a mode register reading signal responsive to the decoded plurality of command signals. The code converter is configured to receive mode setting codes generated based on the decoded plurality of command signals and convert the mode setting codes to serial mode setting codes. The code outputting unit is configured to receive the serial mode setting codes and output the serial mode setting codes to the external source responsive to the mode register reading signal. Systems including the semiconductor memory devices are also provided.

摘要翻译： 提供半导体存储器件。 半导体存储器件包括命令解码器，代码转换器和代码输出单元。 命令解码器被配置为从外部源接收多个命令信号，解码多个命令信号并响应于解码的多个命令信号产生模式寄存器读取信号。 代码转换器被配置为接收基于解码的多个命令信号生成的模式设置代码，并将模式设置代码转换为串行模式设置代码。 代码输出单元被配置为接收串行模式设置代码，并且响应于模式寄存器读取信号将串行模式设置代码输出到外部源。 还提供了包括半导体存储器件的系统。

公开(公告)号：US07133295B2

公开(公告)日：2006-11-07

申请号：US10405485

申请日：2003-04-03

申请人： Dong-Yang Lee

发明人： Dong-Yang Lee

IPC分类号： H01R12/16

CPC分类号： H05K1/141 ,  G11C5/04 ,  H05K2201/10159 ,  H05K2201/10189

摘要： A memory module including at least one memory device mounted on a support member and at least one connect terminal mounted on the support member a distance from an edge of the support member and a memory system including the memory module are provided. The memory device may be a semiconductor device. The connect terminal may be located on at least one surface of the support member, which may be a printed circuit board. The connect terminal may be capable of connecting the memory module to a main board or to other memory modules. Further, the connect terminal may be electrically connected to the memory devices. A buffer may be mounted on the support member a distance from the edge of the support member. A main board including a base member and a second connect terminal may be connected to the memory module to form the memory system.

摘要翻译： 提供一种存储模块，其包括安装在支撑构件上的至少一个存储器装置和安装在所述支撑构件上的距离所述支撑构件的边缘一定距离的至少一个连接端子以及包括所述存储器模块的存储器系统。 存储器件可以是半导体器件。 连接端子可以位于支撑构件的至少一个表面上，该表面可以是印刷电路板。 连接端子可能能够将存储器模块连接到主板或其他存储器模块。 此外，连接端子可以电连接到存储器件。 缓冲器可以从支撑构件的边缘一定距离地安装在支撑构件上。 包括基座构件和第二连接端子的主板可以连接到存储器模块以形成存储器系统。

公开(公告)号：US06650594B1

公开(公告)日：2003-11-18

申请号：US10281342

申请日：2002-10-28

申请人： Jung-Bae Lee ,  Dong-Yang Lee

发明人： Jung-Bae Lee ,  Dong-Yang Lee

IPC分类号： G11C800

CPC分类号： G11C11/4074 ,  G11C5/147 ,  G11C7/22 ,  G11C7/222

摘要： A semiconductor integrated circuit and a memory device capable of selecting power-down exit speed and power-save modes and method thereof are provided. The memory device includes a command decoder for generating a power-down signal in response to a power-down command, a mode register (MRS) for storing power-down exit information, a clock synchronization circuit such as a DLL or PLL circuit for generating an internal clock signal synchronized with an external clock signal, and a controller for controlling the DLL or PLL circuit. At power-down exit of the memory device, the power-down exit information can be selected between a fast wakeup time and a slow wakeup time.

摘要翻译： 提供了能够选择掉电退出速度和省电模式的半导体集成电路和存储器件及其方法。 存储器件包括用于响应于掉电命令产生掉电信号的命令解码器，用于存储掉电退出信息的模式寄存器（MRS），诸如DLL或PLL电路的时钟同步电路，用于产生 与外部时钟信号同步的内部时钟信号，以及用于控制DLL或PLL电路的控制器。 在存储设备的掉电退出时，可以在快速唤醒时间和缓慢的唤醒时间之间选择掉电退出信息。

公开(公告)号：US07058776B2

公开(公告)日：2006-06-06

申请号：US10396933

申请日：2003-03-25

申请人： Dong-Yang Lee

发明人： Dong-Yang Lee

IPC分类号： G06F12/00

CPC分类号： G11C7/109 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087

摘要： A memory for storing data information and/or a controller for controlling read/write operations of the memory based on a source synchronous interface are provided. During the read/write operations, a command and an address are provided to the memory together with the first strobe signal. The memory may latch the command and address in response to the first strobe signal. During a read operation, the memory responds to a received second strobe signal to generate a third strobe signal. The memory outputs data from the memory and the third strobe signal, for example, so that the output data may be latched with the third strobe signal by the memory controller.

摘要翻译： 提供了一种用于存储数据信息的存储器和/或用于基于源同步接口来控制存储器的读/写操作的控制器。 在读/写操作期间，与第一选通信号一起向存储器提供命令和地址。 存储器可以响应于第一选通信号来锁存命令和地址。 在读操作期间，存储器响应接收的第二选通信号以产生第三选通信号。 存储器例如从存储器和第三选通信号输出数据，使得输出数据可以由存储器控制器用第三选通信号锁存。

公开(公告)号：US06965528B2

公开(公告)日：2005-11-15

申请号：US10641637

申请日：2003-08-14

申请人： Jae-Hyeong Lee ,  Jung-Bae Lee ,  Dong-Yang Lee

发明人： Jae-Hyeong Lee ,  Jung-Bae Lee ,  Dong-Yang Lee

IPC分类号： G11C7/00 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

CPC分类号： G11C11/4076 ,  G06F13/1647 ,  G11C7/1045 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory device having a high bus efficiency on a network, an operating method of the memory device, and a memory system including the memory device are provided. The memory device includes banks, a programming register, and a controller. Each of the banks has a plurality of memory cells arranged in a matrix of rows and columns. In a write operation, the programming register stores simultaneous write information on how many banks there are in which data are stored. In a read operation, the controller selects one of the banks subjected to the write operation in response to the simultaneous write information to read out the memory cell data in the selected bank.

摘要翻译： 提供了一种在网络上具有高总线效率的存储器件，存储器件的操作方法以及包括存储器件的存储器系统。 存储器件包括存储体，编程寄存器和控制器。 每个存储体具有以行和列的矩阵排列的多个存储单元。 在写入操作中，编程寄存器存储关于存储了哪些数据的存储器的同时写入信息。 在读取操作中，控制器响应于同时写入信息来选择经过写入操作的存储体之一，以读出所选择的存储体中的存储器单元数据。

公开(公告)号：US20090213659A1

公开(公告)日：2009-08-27

申请号：US12393397

申请日：2009-02-26

申请人： Kyeong-Han Lee ,  Seok-Cheon Kwon ,  Dong-Yang Lee

发明人： Kyeong-Han Lee ,  Seok-Cheon Kwon ,  Dong-Yang Lee

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/26 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C16/08 ,  G11C16/102 ,  G11C16/32 ,  G11C2207/107 ,  G11C2207/2281

摘要： A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

摘要翻译： 一种闪存装置，包括：存储单元阵列; 信号发生器输入第一数据提取信号并输出​​第二数据获取信号; 以及输出缓冲器电路，被配置为与第二数据提取信号的上升沿和下降沿同步地从存储单元阵列输出数据，其中第二数据取出信号与从输出缓冲器电路输出的数据一起输出。

公开(公告)号：US20070088921A1

公开(公告)日：2007-04-19

申请号：US11546625

申请日：2006-10-12

申请人： Joon-Kun Kim ,  Dong-Yang Lee

发明人： Joon-Kun Kim ,  Dong-Yang Lee

IPC分类号： G06F13/00 ,  G11C5/06

CPC分类号： G11C5/06 ,  G11C7/1045

摘要： Semiconductor memory devices are provided. The semiconductor memory device includes a command decoder, a code converter and a code outputting unit. The command decoder is configured to receive a plurality of command signals from an external source, decode the plurality of command signals and generate a mode register reading signal responsive to the decoded plurality of command signals. The code converter is configured to receive mode setting codes generated based on the decoded plurality of command signals and convert the mode setting codes to serial mode setting codes. The code outputting unit is configured to receive the serial mode setting codes and output the serial mode setting codes to the external source responsive to the mode register reading signal. Systems including the semiconductor memory devices are also provided.

摘要翻译： 提供半导体存储器件。 半导体存储器件包括命令解码器，代码转换器和代码输出单元。 命令解码器被配置为从外部源接收多个命令信号，解码多个命令信号并响应于解码的多个命令信号产生模式寄存器读取信号。 代码转换器被配置为接收基于解码的多个命令信号生成的模式设置代码，并将模式设置代码转换为串行模式设置代码。 代码输出单元被配置为接收串行模式设置代码，并且响应于模式寄存器读取信号将串行模式设置代码输出到外部源。 还提供了包括半导体存储器件的系统。

公开(公告)号：US07057950B2

公开(公告)日：2006-06-06

申请号：US10706891

申请日：2003-11-13

申请人： Dong-Yang Lee

发明人： Dong-Yang Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/22 ,  G11C11/4076

摘要： A semiconductor device performs read or write when read or write command with auto-precharge function is input. The semiconductor device does not carry out the auto-precharge operation until a predetermined auto-precharge delay time passes. Therefore, page mode can be performed while using read or write command with auto-precharge function.

摘要翻译： 当输入具有自动预充电功能的读或写命令时，半导体器件执行读或写操作。 在预定的自动预充电延迟时间过去之前，半导体器件不执行自动预充电操作。 因此，可以在使用具有自动预充电功能的读或写命令时执行页模式。