公开(公告)号：US20220272026A1

公开(公告)日：2022-08-25

申请号：US17650960

申请日：2022-02-14

申请人： EFINIX, INC.

发明人： Marcel Gort ,  Brett Grady

IPC分类号： H04L45/122 ,  H04L45/42 ,  H03K19/173 ,  H03K19/17728

摘要： Methods and apparatuses to provide FPGA neighbor output mux direct connections to reduce, and potentially minimize, routing hops are described. Embodiments described herein include the addition of direct connections from one tile to the output muxing of a neighboring tile. An FPGA apparatus includes a plurality of logic block tiles. One or more direct connections extend from one or more logic block tiles of the plurality of logic block tiles to one or more inputs of output multiplexors (muxes) of one or more neighboring logic block tiles. The one or more direct connections are configured to drive one or more wires that start at the one or more neighboring logic block tiles.

公开(公告)号：US20220247397A1

公开(公告)日：2022-08-04

申请号：US17584025

申请日：2022-01-25

申请人： EFINIX, INC.

发明人： Marcel Gort

IPC分类号： H03K5/133 ,  H03K19/17736

摘要： Delay elements and multiplexers are in programmable delay elements. Each programmable delay element has a chain of delay elements to produce successive delays of a clock of the programmable delay element. Each programmable delay element has a first multiplexer to select among an input clock and delay element outputs in the chain of delay elements to produce a skewed clock output of the programmable delay element. In at least a subset of the programmable delay elements, each programmable delay element has a second multiplexer to select among clocks that include a first clock, and a second clock that is from one of the delay elements of another programmable delay element to produce the clock of the programmable delay element.

公开(公告)号：US20240273334A1

公开(公告)日：2024-08-15

申请号：US18169007

申请日：2023-02-14

申请人： EFINIX, INC.

发明人： Yee Hui LEE ,  Ching Lun YAN

IPC分类号： G06N3/02

CPC分类号： G06N3/02

摘要： The present invention relates to neural network accelerator (103) in a field programmable gate array (FPGA) which is based on custom instruction interface of an embedded processor (102) in said FPGA, wherein said neural network accelerator (103) comprises of a command control block (301), at least one neural network layer accelerator (303) and a response control block (305). The amount of neural network layer accelerators (103) that can be implemented can be configured easily (such as adding a new type of layer accelerator (303) to said neural network layer accelerator (103)) in said FPGA, which makes said invention flexible and scalable.

公开(公告)号：US12052160B2

公开(公告)日：2024-07-30

申请号：US17650960

申请日：2022-02-14

申请人： EFINIX, INC.

发明人： Marcel Gort ,  Brett Grady

IPC分类号： H03K19/17728 ,  H03K19/173 ,  H04L45/122 ,  H04L45/42

CPC分类号： H04L45/122 ,  H03K19/1737 ,  H03K19/17728 ,  H04L45/42

摘要： Methods and apparatuses to provide FPGA neighbor output mux direct connections to reduce, and potentially minimize, routing hops are described. Embodiments described herein include the addition of direct connections from one tile to the output muxing of a neighboring tile. An FPGA apparatus includes a plurality of logic block tiles. One or more direct connections extend from one or more logic block tiles of the plurality of logic block tiles to one or more inputs of output multiplexors (muxes) of one or more neighboring logic block tiles. The one or more direct connections are configured to drive one or more wires that start at the one or more neighboring logic block tiles.

公开(公告)号：US20220245315A1

公开(公告)日：2022-08-04

申请号：US17546858

申请日：2021-12-09

申请人： EFINIX, INC.

发明人： Marcel Gort ,  Nima Karimpour-Darav

IPC分类号： G06F30/331 ,  G06F30/327 ,  G06F30/394

摘要： A computer aided design (CAD) system receives a high level coding of a design for a circuit to be implemented in a field programmable gate array (FPGA). The system performs synthesis on the design, to produce a synthesized design. The system generates a routability estimation and a logic usage estimation for the synthesized design. The system determines whether the synthesized design is implementable on a specific FPGA, based on the routability estimation, the logic usage estimation, and available resources of the specific FPGA.

公开(公告)号：US20210042462A1

公开(公告)日：2021-02-11

申请号：US17068456

申请日：2020-10-12

申请人： EFINIX, INC.

发明人： James Schleicher

IPC分类号： G06F30/392 ,  G06F30/394

摘要： A system having design tools and methods for using the same in designing an integrated circuit (IC) are described. In one embodiment, an IC design system, the system comprises one or more processors; and a non-transitory computer readable medium connected to the one or more processors, wherein the non-transitory computer readable medium is configured to store: a first design tool module configured to determine one or more design specifications for a core of an integrated circuit (IC), the IC comprising a plurality of transistors and other components, and a plurality of interconnects between the transistors and the other components, wherein the plurality of transistors and the other components and the plurality of interconnects are formed on a single die, and a second design tool module configured to determine one or more design specifications for a periphery of the IC, the second tool to function independently of the first tool and operable to design constraints for interface placement and configuration of an interface between the core and the periphery of IC.

公开(公告)号：US11791823B2

公开(公告)日：2023-10-17

申请号：US17651175

申请日：2022-02-15

申请人： EFINIX, INC.

发明人： Marcel Gort ,  Brett Grady

IPC分类号： H03K19/17728

CPC分类号： H03K19/17728

摘要： Methods and apparatuses to provide FPGA inter-tile control signal sharing are described. In one embodiment, the FPGA inter-tile muxing for control signals is added in a separate tile. In another embodiment, the control signal muxing is distributed among FPGA tiles and shared using a cascaded configuration.

公开(公告)号：US20220317970A1

公开(公告)日：2022-10-06

申请号：US17389128

申请日：2021-07-29

申请人： EFINIX, INC.

发明人： Ho Man Ho

IPC分类号： G06F7/487 ,  G06F7/485

摘要： A digital signal processor (DSP), which may be implemented as a DSP block in a field programmable gate array (FPGA), includes a fracturable multiplier, a fracturable adder and a fracturable variable shifter. Further included is at least one sign-extension block, to provide for normal mode, dual-fracturing mode and quad-fracturing mode.

公开(公告)号：US20220247413A1

公开(公告)日：2022-08-04

申请号：US17584904

申请日：2022-01-26

申请人： EFINIX, INC.

发明人： Marcel Gort

IPC分类号： H03K19/17728 ,  H03K19/173 ,  G06F7/503

摘要： A field programmable gate array (FPGA) has a 4-LUT (lookup table) that has four stages of multiplexers. The 4-LUT is fracturable. The 4-LUT being fracturable includes the capability to implement multiple LUTs in an instance of FPGA programming for functions from a group that includes adder functions and further functions. The 4-LUT has outputs exposed to programmable connection in accordance with FPGA programming. Outputs of the 4-LUT include an output of a first multiplexer in the third stage, an output of a multiplexer in the second stage, and an output of a multiplexer in the second or third stage of the 4-LUT.

公开(公告)号：US11356101B1

公开(公告)日：2022-06-07

申请号：US17389112

申请日：2021-07-29

申请人： Efinix, Inc.

发明人： Ho Man Ho

IPC分类号： H03K19/17736 ,  H03K19/17732 ,  H03K19/0175

摘要： A digital signal processing block has a first input port, a second input port, a third input port, a cascade input port and an output port. The DSP block may have a cascade output port. The DSP block may have a multiplexer that has selectable output, to the cascade output port, of concatenated inputs from the first input port, the second input port and the third input port. The DSP block may be connectable to another DSP block via a cascade path. The DSP block may have a variable shifter. The DSP block may have a full-width adder and reduced-width input ports.