CIRCUIT ARRANGEMENT WITH INTERFERENCE PROTECTION
    1.
    发明申请
    CIRCUIT ARRANGEMENT WITH INTERFERENCE PROTECTION 有权
    电路布置与干扰保护

    公开(公告)号:US20100219882A1

    公开(公告)日:2010-09-02

    申请号:US12778109

    申请日:2010-05-11

    IPC分类号: H03K5/00

    CPC分类号: H04B15/005

    摘要: A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device coupled to at least the supply line to suppress any interfering signals from being applied to the supply line.

    摘要翻译: 公开了一种具有干扰保护的电路装置,包括电源线和接地线,第一电路和第二电路。 第一和第二电路中的每一个连接到电源线和接地线。 电路装置还包括耦合到至少电源线的阻断装置,以抑制任何干扰信号被施加到电源线。

    Digital PLL (phase-locked loop) frequency synthesizer
    2.
    发明授权
    Digital PLL (phase-locked loop) frequency synthesizer 失效
    数字PLL(锁相环)频率合成器

    公开(公告)号:US06359950B2

    公开(公告)日:2002-03-19

    申请号:US09799669

    申请日:2001-03-05

    IPC分类号: H03D324

    摘要: The circuit compensates for phase error in the case of fractional-N-based PLL frequency synthesizers. All required actuating and reference signals are derived from the VCO frequency of the voltage-controlled oscillator by using an auxiliary phase-locked loop. The circuit is specifically applicable for HF-PLL frequency synthesizers using integrated circuit technology.

    摘要翻译: 在基于分数N的PLL频率合成器的情况下,电路补偿相位误差。 所有需要的启动和参考信号都是通过使用辅助锁相环从压控振荡器的VCO频率得出的。 该电路特别适用于使用集成电路技术的HF-PLL频率合成器。

    Phase-locked loop (PLL) for radio-frequency (RF) signals
    3.
    发明授权
    Phase-locked loop (PLL) for radio-frequency (RF) signals 有权
    用于射频(RF)信号的锁相环(PLL)

    公开(公告)号:US06215362B1

    公开(公告)日:2001-04-10

    申请号:US09327011

    申请日:1999-06-07

    IPC分类号: H03L7089

    CPC分类号: H03L7/0891 H03L7/10 H03L7/185

    摘要: In a PLL circuit, the precharging function necessary for setting a required initial state of a VCO is achieved by an additional precharge pump inserted in parallel with the charge pump, or alternatively by multiplexers and inverters implemented directly with the charge pump. The precharging function being controlled in both cases by two control signals. PLL circuits according to the invention are applied, in particular, in integrated circuits of mobile transceivers, for example for GSM, PCN and PCS.

    摘要翻译: 在PLL电路中,通过与电荷泵并联插入的附加预充电泵,或者通过与电荷泵直接实现的多路复用器和逆变器来实现设定VCO所需的初始状态所需的预充电功能。 预充电功能在两种情况下均由两个控制信号控制。 根据本发明的PLL电路特别地应用于移动收发器的集成电路中,例如用于GSM,PCN和PCS。

    Circuit arrangement with interference protection

    公开(公告)号:US09673913B2

    公开(公告)日:2017-06-06

    申请号:US12778109

    申请日:2010-05-11

    IPC分类号: H03K5/00 H04B15/00

    CPC分类号: H04B15/005

    摘要: A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device coupled to at least the supply line to suppress any interfering signals from being applied to the supply line.

    Phase-control circuit arrangement and method for operating said circuit arrangement
    6.
    发明授权
    Phase-control circuit arrangement and method for operating said circuit arrangement 失效
    用于操作所述电路装置的相位控制电路装置和方法

    公开(公告)号:US07068112B2

    公开(公告)日:2006-06-27

    申请号:US11136232

    申请日:2005-05-24

    IPC分类号: H03L7/087

    CPC分类号: H03L7/10 H03L2207/05

    摘要: A circuit arrangement includes a phase locked loop configured to produce a controlled frequency. The phase locked loop has an actuating input and a control loop output, with it being possible to tap off the frequency at the control loop output. In addition, a frequency meter is provided, which is connected to the control loop output of the phase locked loop. The frequency meter is configured to measure the frequency of the phase locked loop. Finally, a computation unit is provided in order to determine a gradient associated with the phase locked loop and generate a correction value based thereon, wherein the correction value is employed to mitigate a deterioration in the loop bandwidth due to variations in the gradient.

    摘要翻译: 电路装置包括被配置为产生受控频率的锁相环。 锁相环具有启动输入和控制回路输出,可以在控制回路输出端分断出频率。 另外,还提供一个频率计,连接到锁相环的控制回路输出。 频率计配置为测量锁相环的频率。 最后,提供计算单元以便确定与锁相环相关联的梯度并基于此生成校正值,其中采用校正值来减轻由于梯度变化引起的环路带宽的恶化。

    Phase-locked loop with short transient recovery duration and small interference signal component
    7.
    发明授权
    Phase-locked loop with short transient recovery duration and small interference signal component 失效
    具有短暂恢复持续时间和小干扰信号分量的锁相环

    公开(公告)号:US06621356B2

    公开(公告)日:2003-09-16

    申请号:US10113632

    申请日:2002-03-27

    IPC分类号: H03L700

    摘要: In order to shorten the transient recovery duration, the phase-locked loop has a voltage-controlled oscillator providing an oscillator signal to a first frequency divider. The first frequency divider divides the frequency of the oscillator signal, generates a first divider output signal therefrom, and passes it to a phase comparator during the transient recovery duration of the phase-locked loop. Furthermore, a unit is provided, which, after the transient recovery duration of the phase-looped loop, divides the frequency of the first divider output signal and passes it to the phase comparator. The phase comparator compares the first divider output signal with a first reference signal during the transient recovery duration. The phase comparator compares the divided divider output signal with a second reference signal after the transient recovery duration. The output of the phase comparator is connected to the voltage-controlled oscillator via a controllable charge pump.

    摘要翻译: 为了缩短瞬态恢复持续时间,锁相环具有向第一分频器提供振荡器信号的压控振荡器。 第一分频器分频振荡器信号的频率,从其产生第一分频器输出信号,并在锁相环的瞬态恢复持续时间期间将其传送到相位比较器。 此外,提供了一个单元,其在相环环路的瞬态恢复持续时间之后,划分第一分频器输出信号的频率并将其传递给相位比较器。 相位比较器在瞬态恢复持续时间期间将第一分频器输出信号与第一参考信号进行比较。 相位比较器将分频分频器输出信号与瞬态恢复持续时间之后的第二参考信号进行比较。 相位比较器的输出通过可控电荷泵连接到压控振荡器。

    Circuit arrangement with interference protection
    8.
    发明授权
    Circuit arrangement with interference protection 失效
    具有干扰保护的电路布置

    公开(公告)号:US07733165B2

    公开(公告)日:2010-06-08

    申请号:US11711210

    申请日:2007-02-27

    IPC分类号: H03K5/00

    CPC分类号: H04B15/005

    摘要: A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device coupled to at least the supply line to suppress any interfering signals from being applied to the supply line.

    摘要翻译: 公开了一种具有干扰保护的电路装置,包括电源线和接地线,第一电路和第二电路。 第一和第二电路中的每一个连接到电源线和接地线。 电路装置还包括耦合到至少电源线的阻断装置,以抑制任何干扰信号被施加到电源线。