公开(公告)号：US3980897A

公开(公告)日：1976-09-14

申请号：US486450

申请日：1974-07-08

申请人： Edward H. Arnold

发明人： Edward H. Arnold

IPC分类号： H03K3/3562 ,  H03K19/0948 ,  H03K19/08 ,  H03K3/286 ,  H03K3/353 ,  H03K19/20

CPC分类号： H03K3/3562 ,  H03K19/0948

摘要： A first subset of semiconductor devices has an associated first additional device and a first gate output. A second subset of semiconductor devices has an associated second additional device and a second gate output. The first and second subsets are of one conductivity type while the first and second additional devices are of another conductivity type. First logic signals are applied to the first subset for turning on the first subset and the first additional device for producing at the first gate output a first function of the first logic signals. Second logic signals are applied to the second subset for turning on the second subset and the second additional device for producing at the second gate output a second function of the second logic signals.

摘要翻译： 半导体器件的第一子集具有相关联的第一附加器件和第一栅极输出。 半导体器件的第二子集具有相关联的第二附加器件和第二栅极输出。 第一和第二子集是一种导电类型，而第一和第二附加装置是另一导电类型。 第一逻辑信号被施加到第一子集，用于接通第一子集，第一附加装置用于在第一栅极输出产生第一逻辑信号的第一函数。 第二逻辑信号被施加到第二子集以接通第二子集，第二附加装置用于在第二栅极输出产生第二逻辑信号的第二函数。

公开(公告)号：US3979681A

公开(公告)日：1976-09-07

申请号：US527831

申请日：1974-11-27

申请人： Edward H. Arnold

发明人： Edward H. Arnold

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G04D7/12 ,  H03K21/38 ,  H03K21/40 ,  H03K21/32 ,  G04B19/30 ,  G04C3/00

CPC分类号： H03K21/38 ,  G01R31/31701 ,  G01R31/318527 ,  G04D7/12 ,  H03K21/40

摘要： A solid state timepiece having a chain of series connected counters with clock pulses being applied to the first counter in the chain. A reset system is responsive to reset signals and is coupled to the counters for selective resetting of the counters upon application of predetermined reset signals. A decoder system independent of the resetting of the counters detects the state of the reset signals during a predetermined time duration and produces a control signal upon application of selected reset signal states. A control system provides internal control of the timepiece only upon application of the control signal.

摘要翻译： 固态钟表具有串联连接的计数器链，时钟脉冲被施加到链中的第一计数器。 复位系统响应于复位信号，并且耦合到计数器，以在应用预定的复位信号时选择性地重置计数器。 独立于计数器的复位的解码器系统在预定的持续时间内检测复位信号的状态，并在应用所选择的复位信号状态时产生控制信号。 控制系统仅在应用控制信号时提供时钟的内部控制。